參數(shù)資料
型號: KSZ8841-16MQL A6
廠商: Micrel Inc
文件頁數(shù): 62/105頁
文件大?。?/td> 0K
描述: IC MAC CTRLR 8/16BIT 128-PQFP
標準包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
配用: 576-1631-ND - BOARD EVALUATION KSZ8841-16MQL
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
6
M9999-102207-1.6
Bank 16 RXQ Memory Information Register (0x0A): RXMIR....................................................................................... 65
Bank 17 TXQ Command Register (0x00): TXQCR ...................................................................................................... 65
Bank 17 RXQ Command Register (0x02): RXQCR ..................................................................................................... 65
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR ........................................................................................ 66
Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR ....................................................................................... 66
Bank 17 QMU Data Register Low (0x08): QDRL ......................................................................................................... 67
Bank 17 QMU Data Register High (0x0A): QDRH ....................................................................................................... 67
Bank 18 Interrupt Enable Register (0x00): IER ............................................................................................................ 68
Bank 18 Interrupt Status Register (0x02): ISR ............................................................................................................. 69
Bank 18 Receive Status Register (0x04): RXSR ......................................................................................................... 70
Bank 18 Receive Byte Count Register (0x06): RXBC.................................................................................................. 70
Bank 18 Early Transmit Register (0x08): ETXR........................................................................................................... 71
Bank 18 Early Receive Register (0x0A): ERXR ........................................................................................................... 71
Bank 19 Multicast Table Register 0 (0x00): MTR0....................................................................................................... 71
Bank 19 Multicast Table Register 1 (0x02): MTR1....................................................................................................... 72
Bank 19 Multicast Table Register 2 (0x04): MTR2....................................................................................................... 72
Bank 19 Multicast Table Register 3 (0x06): MTR3....................................................................................................... 72
Bank 19 Power Management Control and Status Register (0x08): PMCS .................................................................. 72
Banks 20 – 31: Reserved ............................................................................................................................................. 73
Bank 32 Chip ID and Enable Register (0x00): CIDER ................................................................................................. 73
Bank 32 Chip Global Control Register (0x0A): CGCR ................................................................................................. 74
Banks 33 – 41: Reserved ............................................................................................................................................. 74
Bank 42 Indirect Access Control Register (0x00): IACR .............................................................................................. 75
Bank 42 Indirect Access Data Register 1 (0x02): IADR1 ............................................................................................. 75
Bank 42 Indirect Access Data Register 2 (0x04): IADR2 ............................................................................................. 75
Bank 42 Indirect Access Data Register 3 (0x06): IADR3 ............................................................................................. 75
Bank 42 Indirect Access Data Register 4 (0x08): IADR4 ............................................................................................. 75
Bank 42 Indirect Access Data Register 5 (0x0A): IADR5 ............................................................................................ 75
Bank 43– 44: Reserved ................................................................................................................................................ 75
Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR ....................................................................... 76
Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR......................................................................... 77
Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR............................................................................................... 77
Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR ............................................................................................. 78
Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR............................................................... 78
Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR ..................................................... 78
Bank 46: Reserved ....................................................................................................................................................... 79
Bank 47 PHY1 LinkMD Control/Status (0x00): P1VCT ................................................................................................ 79
Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL ........................................................................ 80
Bank 48: Reserved ....................................................................................................................................................... 80
Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD ................................................................. 81
Bank 49 Port 1 Control Register 4 (0x02): P1CR4....................................................................................................... 82
Bank 49 Port 1 Status Register (0x04): P1SR ............................................................................................................. 83
Banks 50 – 63: Reserved ............................................................................................................................................. 84
MIB (Management Information Base) Counters............................................................................................................... 85
Additional MIB Information ........................................................................................................................................... 86
Absolute Maximum Ratings
(1) ............................................................................................................................................ 87
Operating Ratings
(1) ............................................................................................................................................................ 87
Electrical Characteristics
(1) ................................................................................................................................................ 88
Timing Specifications ......................................................................................................................................................... 89
Asynchronous Timing without using Address Strobe (ADSN = 0) ............................................................................... 89
Asynchronous Timing using Address Strobe (ADSN) .................................................................................................. 90
Asynchronous Timing using DATACSN ....................................................................................................................... 91
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