參數(shù)資料
型號: KSZ8864RMNI
廠商: Micrel Inc
文件頁數(shù): 13/111頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 4PORT 64QFN
特色產(chǎn)品: KSZ8864RMN Ethernet Switches
標準包裝: 348
系列: *
其它名稱: 576-3995
Micrel, Inc.
KSZ8864RMN
April 2012
11
M9999-043012-1.5
Pin Description (Continued)
Pin Number
Pin Name
Type
(1)
Port
Pin Function
(2)
26
SM3RXD2
IPD/O
3
MAC3 Switch MII receive bit 2 and Strap option:
PD (default) = disable back pressure;
PU = enable back pressure.
27
SM3RXD1
IPD/O
3
MAC3 Switch MII/RMII receive bit 1.
Strap option:
PD (default) = drop excessive collision packets;
PU = does not drop excessive collision packets.
28
SM3RXD0
IPD/O
3
MAC3 Switch MII/RMII receive bit 0.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex
mode;
PU = enable for performance enhancement.
29
SM3CRS
IPD/O
3
MAC3 Switch MII carrier sense.
30
GND
Ground with all grounding of die bottom.
31
SM3COL
IPD/O
3
MAC3 Switch MII collision detect.
32
SM4TXEN
IPD
4
MAC4 Switch MII/RMII transmit enable.
33
SM4TXD3
IPD
4
MAC4 Switch MII transmit bit 3.
34
SM4TXD2
IPD
4
MAC4 Switch MII transmit bit 2.
35
SM4TXD1
IPD
4
MAC4 Switch MII/RMII transmit bit 1.
36
SM4TXD0
IPD
4
MAC4 Switch MII/RMII transmit bit 0.
37
SM4TXC/SM4REFCLK
I/O
4
MAC4 Switch MII transmit clock:
Input: SW4-MII MAC mode clock.
Input: SW4-RMII reference clock, please also see the strap-in pin
P1LED1 for the clock mode and normal mode.
Output: SW4-MII PHY modes.
38
VDDIO
P
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
39
SM4RXC
I/O
4
MAC4 Switch MII Receive clock:
Input: SW4-MII MAC mode.
Output: SW4-MII PHY mode.
Output: SW4-RMII 50MHz reference clock (the device is default clock
mode, the clock source comes from X1/X2 pins 25MHz crystal).
When set the device as normal mode (the chip’s clock source comes
from SM4TXC), the SM4RXC reference clock output should be
disabled by the register 87. Please also see the strap-in pin P1LED1
for the selection of the clock mode and normal mode.
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