參數(shù)資料
型號(hào): KSZ8873FLL
廠商: Micrel Inc
文件頁(yè)數(shù): 47/115頁(yè)
文件大?。?/td> 0K
描述: IC ETHERNET SW 3PORT 64LQFP
產(chǎn)品培訓(xùn)模塊: KSZ8873 Ethernet Switches
特色產(chǎn)品: KSZ8873 Ethernet Switch Controller
標(biāo)準(zhǔn)包裝: 160
控制器類(lèi)型: 以太網(wǎng)開(kāi)關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤(pán)
其它名稱(chēng): 576-3631
KSZ8873FLL-ND
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Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
37
Revision 1.6
QoS Priority Support
The KSZ8873MLL/FLL/RLL provides Quality of Service (QoS) for applications such as VoIP and video conferencing.
Offering four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is the
highest priority queue and Queue 0 is the lowest priority queue. Bit [0] of Registers 16, 32 and 48 is used to enable split
transmit queues for ports 1, 2 and 3, respectively. If a port's transmit queue is not split, high priority and low priority
packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the four
priority queues. This global option is set and explained in bit [3] of Register 5.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets received at
the high priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the
corresponding transmit queue is split. Bits [4:3] of Registers 16, 32 and 48 are used to enable port-based priority for ports
1, 2 and 3, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8873MLL/FLL/RLL examines the ingress (incoming) packets to determine whether they
are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping”
value, as specified by the Registers 12 and 13. The “priority mapping” value is programmable.
Figure 6 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Preamble
DA
TCI
8
6
2
length
LLC
Data
FCS
2
46-1500
4
1
Tagged Packet Type
(8100 for Ethernet)
802.1p
CF
I
VLAN ID
Bytes
Bits
16
3
12
802.1q VLAN Tag
2
SA
VPID
Figure 6. 802.1p Priority Field Format
802.1p-based priority is enabled by bit [5] of Registers 16, 32 and 48 for ports 1, 2 and 3, respectively.
The KSZ8873MLL/FLL/RLL provides the option to insert or remove the priority tagged frame's header at each individual
egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field
(TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit [2] of the port registers control 0 and the Register 194 to select which source port (ingress
port) PVID can be inserted on the egress port for ports 1, 2 and 3, respectively. At the egress port, untagged packets are
tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36} and {51,52}
for ports 1, 2 and 3, respectively and the source port VID has to be inserted at selected egress ports by bit[5:0] of register
194. The KSZ8873MLL/FLL/RLL will not add tags to already tagged packets.
Tag Removal is enabled by bit [1] of Registers 16, 32 and 48 for ports 1, 2 and 3, respectively. At the egress port, tagged
packets will have their 802.1Q VLAN Tags removed. The KSZ8873MLL/FLL/RLL will not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
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