參數(shù)資料
型號(hào): KSZ8895MQ
廠商: Micrel Inc
文件頁(yè)數(shù): 80/119頁(yè)
文件大小: 0K
描述: IC ETHERNET SW 5PORT 128-PQFP
標(biāo)準(zhǔn)包裝: 66
控制器類(lèi)型: 以太網(wǎng)開(kāi)關(guān)控制器
接口: MII
電源電壓: 1.8V,2.5V,3.3V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤(pán)
配用: 576-3871-ND - BOARD EVALUATION FOR KSZ8895MQ
其它名稱(chēng): 576-3753
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Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Global Registers (Continued)
Address
Name
Description
Mode
Default
Register 12 (0x0C): Global Control 10
7
Reserved
RO
0
6
Satus of device with RMII
interface at clock mode or
normal mode, default is
clock mode with 25MHz
Crystal clock from pins
X1/X2
(used for RMII of the
KSZ8895RQ only)
1 = The device is in clock mode when use RMII
interface, 25 MHz Crystal clock input as clock source
for internal PLL. This internal PLL will provide the 50
MHz output on the pin SMRXC for RMII reference
clock (Default).
0 = The device is in normal mode when use SW4-RMII
interface and 50 MHz clock input from external clock
through pin SM4TXC as device’s clock source and
internal PLL clock source from this pin not from the
25MHz crystal.
Note: This bit is set by strap option only. Write to this
bit has no effect on mode selection.
Note: The normal mode is used in SW5-RMII interface
reference clock from external.
RO
1
Pin LED[2][2]
strap option.
PD(0): Select
SW5-RMII at
normal mode to
receive external
50MHz RMII
reference clock
PU(1): (default)
Select SW5-
RMII at clock
mode, RMII
output 50MHz
Note: LED[2][2]
has internal pull-
up.
5–4
CPU interface clock select
Select the internal clock speed for SPI, MDI interface:
00 = 41.67MHz (SPI up to 6.25MHz, MDC up to
6MHz)
01 = 83.33MHz Default (SPI SCL up to 12.5MHz,
MDC up to 12MHz)
10 = 125MHz (for hign speed SPI about 25MHz)
11 = Reserved
R/W
01
3
Reserved
N/A Do not change.
RO
0
2
Enable restore preamble
This bit is to enable PHY5, when in 10BT mode, to
restore preamble before sending data on P5-MII
interface.
1 = Enable PHY5 to restore preamble.
0 = Disable PHY5 to restore preamble.
R/W
1
Tail Tag Enable
Tail Tag feature is applied for Port 5 only.
1 = Insert 1 Byte of data right before FCS.
0 = Do not insert.
R/W
0
Pass Flow Control Packet
1 = Switch will not filter 802.1x “flow control” packets.
0 = Switch will filter 802.1x “flow control” packets.
R/W
0
Register 13 (0x0D): Global Control 11
7–0
Factory Testing
N/A Do not change.
RO
00000000
Register 14 (0x0E): Power Down Management Control 1
7
Reserved
N/A Do not change.
RO
0
6
Reserved
N/A Do not change.
RO
0
March 12, 2014
63
Revision 1.7
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