參數(shù)資料
型號: KSZ8993
廠商: Micrel Inc
文件頁數(shù): 6/35頁
文件大?。?/td> 0K
描述: IC SWITCH 10/100 3PORT 128PQFP
標(biāo)準包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-1032
KS8993
Micrel
KS8993
14
May 2005
Group
I/O Names
Active Status
Description
PRSEL[1:0]
H
Selects queue servicing if using split transmit queues. Use the table below to select
desired servicing. Note that this selection effects all split transmit queue ports in the
same way.
PRSEL
1
0
Priority Selection
L
Transmit all high priority before low priority (default)
L
H
Transmit high priority at 10:1 ratio
H
L
Transmit high priority at 5:1 ratio
H
Transmit high priority at 2:1 ratio
CTRL
X1
Clock
External crystal or clock input
X2
Clock
Used when other polarity of crystal is needed. This is unused for a normal clock input.
RST#
L
System reset
TEST
TESTEN
H
Factory test input - pull low
SCANEN
H
Factory test input - pull low
AOUT
H
Factory test output - leave open
MUX[1:2]
H
Mux[1]
Mux[2]
Float
Default for factory test purpose
1
Float
TX Disable Port 1
0
Float
TX Disable Port 2
Float
1
Power Down Port 3
Special note: all other combinations are not allowed
TEST[1:2]
H
Test[1]
Test[2]
Float
Default for factory test purpose
Float
0
Far End Fault Disable
Special note: all other combinations are not allowed .
PWR
VDD_RX[1:3]
2.5V for receiver
GND_RX[1:3]
Ground for receiver
VDD_TX[1:3]
2.5V for transmit circuitry
GND_TX[1:3]
Ground for transmit circuitry
VDD_RCV[1:3]
2.5V for clock recovery circuitry
GND_RCV[1:3]
Ground for clock recovery
VDD_PLL
2.5V for phase locked loop circuitry
GND_PLL
Ground for phase locked loop circuitry
GND_ANA
Analog ground
GND_BG
Analog ground
VDD_BG
2.5V for analog circuits
VDD
2.5V for core digital circuitry
VDD_IO
2.5V or 3.3V for MII interface, LEDs and other digital I/O
GND
Ground for digital circuitry
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PDF描述
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