參數(shù)資料
型號： KSZ8993MLI
廠商： Micrel Inc
文件頁數(shù)： 8/86頁
文件大?。?/td> 0K
描述： IC SWITCH 10/100 3PORT 128-PQFP
標準包裝： 66
系列： *
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
其它名稱： 576-3350
Micrel, Inc.
KSZ8993M/ML
October 2008
16
M9999-020606
Pin Number
Pin Name
Type
(1)
Description
100
101
PS1
PS0
Ipd
Serial bus configuration pins to select mode of access to
KSZ8993M internal registers.
[PS1, PS0] = [0, 0] — I
2C master (EEPROM) mode
(If EEPROM is not detected, the power-up default values of
the KSZ8993M internal registers will be used.)
Interface Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL
O
I
2C clock
SDA
I/O
I
2C data I/O
SPIS_N
Ipu
Not used
[PS1, PS0] = [0, 1] — I
2C slave mode
The external I
2C master will drive the SCL clock.
The KSZ8993M device addresses are:
1011_1111
<read>
1011_1110
<write>
Interface Signals
Type
Description
SPIQ
O
Not used (tri-stated)
SCL
I
2C clock
SDA
I/O
I
2C data I/O
SPIS_N
Ipu
Not used
[PS1, PS0] = [1, 0] — SPI slave mode
Interface Signals
Type
Description
SPIQ
O
SPI data out
SCL
I
SPI clock
SDA
I
SPI data In
SPIS_N
Ipu
SPI chip select
[PS1, PS0] = [1, 1] – SMI-mode
In this mode, the KSZ8993M provides access to all its internal
8 bit registers through its MDC and MDIO pins.
Note:
When (PS1, PS0)
≠ (1,1), the KSZ8993M provides access to
its 16 bit MIIM registers through its MDC and MDIO pins.
102
103
PV31
PV32
Ipu
Port 3 port-based VLAN mask bits – Use to select which
ports may transmit packets received on port 3.
PV31 = 1, port 1 may transmit packets received on port 3
PV31 = 0, port 1 will not transmit any packets received on
port 3
PV32 = 1, port 2 may transmit packets received on port 3
PV32 = 0, port 2 will not transmit any packets received on
port 3
Note:
1. I = Input.
Ipu = Input w/ internal pull-up.
I/O = Bi-directional.
O= Output.
Ipd = Input w/ internal pull-down.
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