Type(1) Port Pin Function 59 VDDIO P" />
參數(shù)資料
型號(hào): KSZ8995MI
廠商: Micrel Inc
文件頁數(shù): 3/76頁
文件大?。?/td> 0K
描述: IC SWITCH 5-PORT 10/100 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-2127
KSZ8995MI-ND
June 2009
11
M9999-062309
KS8995M
Micrel, Inc.
Pin Number
Pin Name
Type(1)
Port
Pin Function
59
VDDIO
P
3.3V digital V
DD for digital I/O circuitry
60
PMRXC
O
5
PHY[5] MII receive clock. PHY mode MII
61
PMRXDV
Ipd/O
5
PHY[5] MII receive data valid
62
PMRXD3
Ipd/O
5
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
63
PMRXD2
Ipd/O
5
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
64
PMRXD1
Ipd/O
5
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
65
PMRXD0
Ipd/O
5
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
66
PMRXER
Ipd/O
5
PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
67
PCRS
Ipd/O
5
PHY[5] MII carrier sense. Strap option for port 4 only. See
“Register 76.”
PD (default) = Force half-duplex if auto-negotiation is disabled or fails.
PU = Force full-duplex if auto-negotiation is disabled or fails.
68
PCOL
Ipd/O
5
PHY[5] MII collision detect. Strap option for port 4 only.
See
“Register 66.” PD (default) = No force flow control. PU = Force
flow control.
69
SMTXEN
Ipd
Switch MII transmit enable
70
SMTXD3
Ipd
Switch MII transmit bit 3
71
SMTXD2
Ipd
Switch MII transmit bit 2
72
SMTXD1
Ipd
Switch MII transmit bit 1
73
SMTXD0
Ipd
Switch MII transmit bit 0
74
SMTXER
Ipd
Switch MII transmit error
75
SMTXC
I/O
Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.
76
GNDD
Gnd
Digital ground
77
VDDIO
P
3.3V digital V
DD for digital I/O circuitry
78
SMRXC
I/O
Switch MII receive clock. Input in MAC mode, output in PHY mode MII.
79
SMRXDV
Ipd/O
Switch MII receive data valid
80
SMRXD3
Ipd/O
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
81
SMRXD2
Ipd/O
Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-
duplex mode; PU = Switch MII in half-duplex mode.
Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
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