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參數(shù)資料
| 型號： | KSZ8995XA |
| 廠商： | MICREL INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | Integrated 5-Port 10/100 QoS Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PQFP128 |
| 封裝： | LEAD FREE, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 14/51頁 |
| 文件大小： | 305K |
| 代理商： | KSZ8995XA |
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KS8995XA
Micrel, Inc.
M9999-051305
14
May 2005
Pin Number
96
95
94
93
92
91
Pin Name
LED3-2
LED4-0
LED4-1
LED4-2
LED5-0
LED5-1
Type
(1)
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Ipu/O
Port
3
4
4
4
5
5
Pin Function
(2)
LED indicator 2.
LED indicator 0.
LED indicator 1.
LED indicator 2.
LED indicator 0.
LED indicator 1. Strap option: PU (default): enable PHY MII I/F
Pd: tristate all PHY MII output. See “Pin# 86 SCONF1.”
LED indicator 2. Aging setup. See “Aging” section.
Switch or PHY[5] MII management data clock.
Switch or PHY[5] MII management data I/O.
No connect. Factory test pin.
No connect. Factory test pin.
PHY[5] MII collision detect/ Force flow control. See “Register 18.”
PHY[5] MII carrier sense/Force duplex mode. See “Register 28.”
PHY[5] MII receive clock. PHY mode MII.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
PHY[5] MII receive data valid.
PHY[5] MII receive error. Strap option: PD (default) = packet size 1518/
1522 bytes; PU = 1536 bytes.
PHY[5] MII transmit clock. PHY mode MII.
PHY[5] MII transmit bit 0.
PHY[5] MII transmit bit 1.
PHY[5] MII transmit bit 2.
PHY[5] MII transmit bit 3.
PHY[5] MII transmit enable.
PHY[5] MII transmit error.
No connect or pull down.
No connect or pull down.
90
107
108
45
46
68
67
60
65
LED5-2
MDC
MDIO
NC / MUX1
NC / MUX2
PCOL
PCRS
PMRXC
PMRXD0
Ipu/O
Ipu
Ipu/O
5
All
All
I
I
5
5
5
5
Ipd/O
Ipd/O
O
Ipd/O
64
PMRXD1
Ipd/O
5
63
PMRXD2
Ipd/O
5
62
PMRXD3
Ipd/O
5
61
66
PMRXDV
PMRXER
Ipd/O
Ipd/O
5
5
57
55
54
53
52
51
56
114
113
PMTXC
PMTXD0
PMTXD1
PMTXD2
PMTXD3
PMTXEN
PMTXER
PS0
PS1
O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
5
5
5
5
5
5
5
Notes:
1. P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
2. PU = Strap pin pull-up.
PD = Strap pull-down.
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| KSZ8995XA4 | 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
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