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參數(shù)資料
| 型號： | KSZ8995XA |
| 廠商： | MICREL INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | Integrated 5-Port 10/100 QoS Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PQFP128 |
| 封裝： | LEAD FREE, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 39/51頁 |
| 文件大小： | 305K |
| 代理商： | KSZ8995XA |
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May 2005
39
M9999-051305
KS8995XA
Register 46 (0x2E): Port 2 Status 0
Register 62 (0x3E): Port 3 Status 0
Register 78 (0x4E): Port 4 Status 0
Register 94 (0x5E): Port 5 Status 0
Address
7
Micrel, Inc.
Name
MDIX status
Description
1 = MDI.
0 = MDI-X.
1 = AN done.
0 = AN not done.
1 = link good.
0 = link not good.
1 = link partner flow control capable.
0 = link partner not flow control capable.
1 = link partner 100BT full-duplex capable.
0 = link partner not 100BT full-duplex capable.
1 = link partner 100BT half-duplex capable.
0 = link partner not 100BT half-duplex capable.
1 = link partner 10BT full-duplex capable.
0 = link partner not 10BT full-duplex capable.
1 = link partner 10BT half-duplex capable.
0 = link partner not 10BT half-duplex capable.
Mode
RO
Default
0
6
AN done
RO
0
5
Link good
RO
0
4
Partner flow
control capability
Partner 100BT
full-duplex capability
Partner 100BT
half-duplex capability
Partner 10BT
full-duplex capability
Partner 10BT
half-duplex capability
RO
0
3
RO
0
2
RO
0
1
RO
0
0
RO
0
Register 31 (0x1F): Port 1 Control 14
Register 47 (0x2F): Port 2 Control 14
Register 63 (0x3F): Port 3 Control 14
Register 79 (0x4F): Port 4 Control 14
Register 95 (0x5F): Port 5 Control 14
Address
7
Name
PHY loopback
Description
1 = perform PHY loopback, i.e. loopback MAC’s Tx
back to Rx.
0 = normal operation.
1 = perform remote loopback, i.e. loopback PHY’s Rx
back to Tx.
0 = normal operation.
1 = electrical isolation of PHY from MII and TX+/TX-.
0 = normal operation.
1 = PHY soft reset.
0 = normal operation.
1 = force link in the PHY.
0 = normal operation.
N/A
1 = far end fault status detected.
0 = no far end fault status detected.
Mode
R/W
Default
0
6
Remote loopback
R/W
0
5
PHY isolate
R/W
0
4
Soft reset
R/W
0
3
Force link
R/W
0
2-1
0
Reserved
Far end fault
RO
RO
0
0
Advanced Control Registers
The IPv4 TOS priority control registers implement a fully decoded 64 bit differentiated services code point (DSCP) register used
to determine priority from the 6 bit TOS field in the IP header. The most significant 6 bits of the TOS field are fully decoded into
64 possibilities, and the singular code that results is compared against the corresponding bit in the DSCP register. If the register
bit is a 1, the priority is high; if it is a 0, the priority is low.
Address
Register 96 (0x60): TOS Priority Control Register 0
7-0
Name
Description
Mode
Default
DSCP[63:56]
R/W
00000000
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| KSZ8995XA4 | 功能描述:IC SWITCH 5-PORT 10/100 128PQFP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
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