參數(shù)資料
型號: KSZ9021GQI
廠商: Micrel Inc
文件頁數(shù): 10/59頁
文件大小: 0K
描述: TXRX GIG ETH GMII/MII 128-PQFP
標(biāo)準(zhǔn)包裝: 66
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
其它名稱: 576-3790
Micrel, Inc.
KSZ9021GQ
September 2010
18
M9999-091010-1.2
Strapping Options
Pin Number
Pin Name
Type
(1)
Pin Function
42
43
44
45
48
PHYAD4
PHYAD3
PHYAD2
PHYAD1
PHYAD0
I/O
The PHY Address, PHYAD[4:0], is latched at power-up / reset and is configurable to
any value from 1 to 31. Each PHY address bit is configured as follows:
Pull-up = 1
Pull-down = 0
78
83
88
89
MODE3
MODE2
MODE1
MODE0
I/O
The MODE[3:0] strap-in pins are latched at power-up / reset and are defined as
follows:
MODE[3:0]
Mode
0000
Reserved – not used
0001
GMII / MII Mode
0010
Reserved – not used
0011
Reserved – not used
0100
NAND Tree Mode
0101
Reserved – not used
0110
Reserved – not used
0111
Chip Power Down Mode
1000
Reserved – not used
1001
Reserved – not used
1010
Reserved – not used
1011
Reserved – not used
1100
Reserved – not used
1101
Reserved – not used
1110
Reserved – not used
1111
Reserved – not used
90
CLK125_EN
I/O
CLK125_EN is latched at power-up / reset and is defined as follows:
Pull-up = Enable 125MHz Clock Output
Pull-down = Disable 125MHz Clock Output
Pin 107 (CLK125_NDO) provides the 125MHz reference clock output option for use
by the MAC.
Notes:
1. I/O = Bi-directional.
2. Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during power-up or reset,
and consequently cause the PHY strap-in pins on the GMII/MII signals to be latched to the incorrect configuration. In this case, it is
recommended to add external pull-ups/pull-downs on the PHY strap-in pins to ensure the PHY is configured to the correct pin strap-in mode.
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