參數(shù)資料
型號: KSZ9021GQI
廠商: Micrel Inc
文件頁數(shù): 18/59頁
文件大?。?/td> 0K
描述: TXRX GIG ETH GMII/MII 128-PQFP
標準包裝: 66
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
其它名稱: 576-3790
Micrel, Inc.
KSZ9021GQ
September 2010
25
M9999-091010-1.2
Auto-Negotiation Interval Timers
Time Duration
Transmit Burst interval
16 ms
Transmit Pulse interval
68 us
FLP detect minimum time
17.2 us
FLP detect maximum time
185 us
Receive minimum Burst interval
6.8 ms
Receive maximum Burst interval
112 ms
Data detect minimum interval
35.4 us
Data detect maximum interval
95 us
NLP test minimum interval
4.5 ms
NLP test maximum interval
30 ms
Link Loss time
52 ms
Break Link time
1480 ms
Parallel Detection wait time
830 ms
Link Enable wait time
1000 ms
Table 2. Auto-Negotiation Timers
GMII Interface
The Gigabit Media Independent Interface (GMII) is compliant to the IEEE 802.3 Specification. It provides a common
interface between GMII PHYs and MACs, and has the following key characteristics:
Pin count is 24 pins (11 pins for data transmission, 11 pins for data reception, and 2 pins for carrier and collision
indication).
1000Mbps is supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 8-bit wide, a byte.
In GMII operation, the GMII pins function as follow:
The MAC sources the transmit reference clock, GTX_CLK, at 125MHz for 1000Mbps.
The PHY recovers and sources the receive reference clock, RX_CLK, at 125MHz for 1000Mbps.
TX_EN, TXD[7:0] and TX_ER are sampled by the KSZ9021GQ on the rising edge of GTX_CLK.
RX_DV, RXD[7:0], and RX_ER are sampled by the MAC on the rising edge of RX_CLK.
CRS and COL are driven by the KSZ9021GQ and are not required to transition synchronously with respect to
either GTX_CLK or RX_CLK.
The KSZ9021GQ combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/1000
Mbps speed. After power-up or reset, the KSZ9021GQ is configured to GMII/MII mode if the MODE[3:0] strap-in pins are
set to 0001. See Strapping Options section.
The KSZ9021GQ has the option to output a low jitter 125MHz reference clock on CLK125_NDO (pin 107). This clock
provides a lower cost reference clock alternative for GMII/MII MACs that require a 125MHz crystal or oscillator. The
125MHz clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9021GQ provides a dedicated transmit clock input pin for GMII mode, defined as follow:
GTX_CLK (input, pin 65):
Sourced by MAC in GMII mode for 1000Mbps speed
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