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參數(shù)資料
| 型號(hào)： | L64222 |
| 廠商： | LSI CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大小： | 248K |
| 代理商： | L64222 |
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22
L64222 DVD Audio/Video Decoder
Figure 4
PLLVDD Decoupling Circuit
PLLVSS
PLL Ground
Input
+ 2.5 V return for the on-chip PLL for deriving the 81 MHz
SDRAM clock. This input must be isolated from the digital
ground plane and only connected at the voltage regulator.
It should be decoupled from the PLLVDD pin.
PLLVDD_2
PLL1 Power Supply
Input
+ 2.5 V input to PLL1 in the ACLK generator. This input
must be isolated from the digital power plane with the
lter shown in Figure 4 and only connected at the voltage
regulator.
PLLVSS_2
PLL1 Ground
Input
+ 2.5 V return for PLL1. This input must be isolated from
the digital ground plane and only connected at the
voltage regulator. It should be decoupled from the
PLLVDD pin.
PLLVDD_3
PLL2 Power Supply
Input
+ 2.5 V input to PLL2 in the ACLK generator. This input
must be isolated from the digital power plane with the
lter shown in Figure 4 and only connected at the voltage
regulator.
PLLVSS_3
PLL2 Ground
Input
+ 2.5 V return for PLL1. This input must be isolated from
the digital ground plane and only connected at the
voltage regulator. It should be decoupled from the
PLLVDD pin.
Miscellaneous and Test Interfaces
IDDQ
Test Mode
Input
Test mode pin. This should be tied to VSS in the system
for normal operation.
VDD
Ferrite Bead
PLLVSS
1 mF
10 mF
PLLVDD
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