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參數(shù)資料
| 型號： | L64222 |
| 廠商： | LSI CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 248K |
| 代理商： | L64222 |
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L64222 DVD Audio/Video Decoder
23
STANDBY
Standby Mode
Input
Asserting this signal places the L64222 in a low-power
standby mode. When STANDBY is deasserted, the
RESETn input should be asserted to place the chip in a
known state.
RESETn
Reset
Input
When RESETn is asserted, the L64222 resets its internal
microcontroller, FIFO controllers, state machines, and
registers. The minimum RESETn pulse width is eight
cycles of SYSCLK (8/27 MHz = 300 ns). SYSCLK and
the selected audio clock (ACLK_32, ACLK_441,
ACLK_48, or the internal ACLK) must be running during
reset.
SYSCLK
Device Clock
Input
Device clock has a nominal frequency of 27 MHz. Picture
reconstruction and video timing are referenced with
respect to this clock. SYSCLK also drives the PLL to
generate the 81 MHz clock for the SDRAM interface and
the selectable Audio SYSCLK.
TM[2:0]
Test Mode
Input
These inputs are used by LSI Logic during manufacturing
test. They are not exercised in a customer system. They
should all be tied to VSS in the system.
ZTEST
Test Mode
Input
Test mode pin. This should be tied to VDD in the system
for normal operation.
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