參數(shù)資料
型號(hào)： L64222
廠(chǎng)商： LSI CORP
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 5/32頁(yè)
文件大?。?/td> 248K
代理商： L64222
L64222 DVD Audio/Video Decoder
13
DTACKn/RDYn
Data Acknowledge/Data Ready
3-State Output
DTACKn - Motorola Mode
The L64222 asserts this signal to indicate to the external
host that the current bus transaction (read or write) can
be completed. DTACKn is 3-stated if CSn is not asserted.
The bus cycle is terminated if the L64222 deasserts
DTACKn before the cycle is completed.
RDYn - Intel Mode
The L64222 asserts this signal to indicate to the external
host that the current bus transaction (read or write) can
be completed. RDYn is 3-stated if CSn is not asserted.
The bus cycle is terminated if the L64222 deasserts
RDYn before the cycle is completed.
WAITn
Wait
3-State Output
This signal may be used instead of DTACKn/RDYn by
hosts that require an inverted sense. The L64222 asserts
WAITn to indicate that its Host Interface is busy with a
read or write bus cycle and it deasserts it when the
current cycle is completed. WAITn is 3-stated when CSn
is not active.
INTRn
Interrupt
OD Output
INTRn is an active-LOW, open-drain, output signal. The
L64222 asserts this signal to alert the host that an
unmasked interrupt condition has occurred in the chip.
The host must read registers 0 through 4 to determine
the cause of the interrupt, take the appropriate action,
and set the Clear Interrupt Pin bit in Register 6 to
deassert INTRn.
DREQn
DMA Transfer Request
Output
The L64222 asserts this signal when it is ready to receive
a new byte of data from or transmit a new byte of data to
an external DMA controller. The state of DREQn reects
the condition of internal read and write FIFOs. For DMA
write cycles, DREQn is deasserted when the write FIFO
is not near full (more than one space left) and deasserted
when the FIFO is near full. For read cycles, DREQn is
asserted when the read FIFO is not near empty (more
than one space lled) and deasserted when the FIFO is
near empty. The maximum transfer rate over this
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