參數(shù)資料
型號(hào)： L64724QC
廠商： LSI CORP
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 23/32頁(yè)
文件大?。?/td> 338K
代理商： L64724QC
L64724 Satellite Receiver
3
Features and Benets
Typical Application
A typical application of the L64724 is satellite digital TV reception in
accordance with the DVB 1110 Rev. 7 standard. Figure 2 shows the
Supports DVB and DSS sys-
tem specications.
BPSK/QPSK demodulation
rates from 1 to 45 Mbaud.
Matched lter (square root
raised cosine lter with roll off
factor of 20% or 35%).
Anti-aliasing lters for opera-
tion from 1 to 45 MBaud with-
out switching external SAW
lters or the need for low-pass
lters.
On-chip digital clock synchro-
nization.
On-chip digital carrier syn-
chronization, featuring a fre-
quency sweep capability for
signal acquisition.
Auto-acquisition demodulator
mode and tuner control
through an on-chip microcon-
troller.
Integrated phase-locked loop
(PLL) for clock synthesis,
allowing the use of a funda-
mental mode crystal.
Dual ADC.
Fast channel switching mode.
Power estimation for AGC
control.
Programmable Viterbi decoder
module for rates 1/2, 2/3, 3/4,
5/6, 6/7, and 7/8.
(204/188), (146/130)
Reed-Solomon decoder.
Auto-synchronization for Viterbi
decoder.
Programmable synchronization
for deinterleaver, Reed-Solomon
decoder, and descrambler.
Bit error monitoring for channel
performance measurements.
Depth 12 convolutional
deinterleaver.
Serial host interface compatible
with the LSI Logic Serial Control
bus interface.
Power-down mode.
On-chip microcontrolled acquisi-
tion and tracking, eliminating
microcontroller interaction, and
simplifying software develop-
ment.
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