參數(shù)資料
型號(hào)： L64733C-48
廠商： LSI CORP
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： TQFP-48
文件頁(yè)數(shù)： 14/52頁(yè)
文件大?。?/td> 552K
代理商： L64733C-48
L64733C/L64734 Tuner and Satellite Receiver Chipset
21
The FDOUB pin is set as shown below; Fswitch is the
frequency that disables or enables the frequency doubler.
MODp, MODn Modulus Selector
Output
The MODp and MODn signals are low-voltage differential
signals from the L64734 of modulus selector
programmable counter (A). PSOUT clocks these signals.
When the MODp signal is positive with respect to the
MODn signal, divide-by-32 is selected at the dual
modulus prescaler on the L64733C Tuner IC. When
MODp is negative with respect to MODn, divide-by-33 is
selected. The counter A can be programmed to count
down from a particular value by register bit programming.
PLLINp, PLLINn
PLL Differential Counter M
Output
The PLLINp and PLLINn signals are low-voltage
differential signals from the L64734 programmable
synthesizer counter (M). PSOUT clocks these signals.
PLLINp is positive with respect to PLLINn for one PSOUT
cycle. The repetition rate is 0.5 MHz for a 4 MHz
reference crystal. The counter M can be programmed to
count down from a particular value by register bit
programming.
PSOUTp, PSOUTn
Prescaler Output
Output
The PSOUTp and PSOUTn signals are differential
signals to the L64734 from the L64733C. The
programmable counters on the L64734 are clocked on
the rising edge of the PSOUT signal.
In the external PLL mode (LOBUF = HIGH), these signals
come from the LO buffer, for which the LODIV signal sets
the divider ratio.
RESO_LVDS
LVDS Buffers Precision Resistor
Output
The RESO_LVDS output must be connected to a resistor
(6.8 k
, which controls the swing of the LVDSOUT
Frequency
FDOUB
APR 79[6]
TRI
APR 79[2]
FDOUB
Pin
925 MHz–Fswitch
0
LOW
Fswitch–1680 MHz
1
3-state
1680–2175 MHz
1
0
HIGH
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L64734 制造商:LSI 制造商全稱:LSI 功能描述:Tuner and Satellite Receiver Chipset
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