L64733C/L64734 Tuner and Satellite Receiver Chipset
17
Control Signals Interface
The Control Signals Interface controls the operation of the L64734 and
is not associated with any particular interface.
IDDTN
Test
Input
The IDDTN pin is an LSI Logic internal test pin. Tie the
IDDTN pin LOW for normal operation.
RESET
Reset
Input
This active-HIGH signal resets all internal data paths.
Reset timing is asynchronous to the device clocks. Reset
does not affect the conguration registers.
XCTR_IN
Control Input
Input
The XCTR_IN pin is an external input control pin. It is
sensed by reading the XCTR_IN register bit.
XCTR[3]
Control Output/Sync Status Flag
Output
The XCTR[3] signal indicates the synchronization status
for one of three synchronization modules in the L64734
or the XCTR[3] eld in Group 4, APR 55. The three
modules are the Viterbi Decoder, Reed-Solomon
Deinterleaver (DI/RS), and Descrambler. For each of the
three synchronization outputs, the asserted XCTR[3]
signal indicates that synchronization is achieved for the
sync module chosen using the SSS[1:0] register bits.
When deasserted, the signal indicates an
out-of-synchronization condition.
XCTR[2:0]
Output Control
Output
The XCTR[2:0] pins are external output control pins.
They are set by programming particular register bits.
XCTR[2] is mapped to CPG1 and XCTR[0] is multiplexed
with CPG2 when used with the L64733C Tuner IC. When
the on-chip serializer generates a serial 2- or 3-wire
protocol on the XCTR[2:0] pins, the mapping is XCTR[2]
= EN, XCTR[1] = SCL, and XCTR[0] = SDA.
Analog-to-Digital Converter (ADC) Interface
The ADC module converts the incoming IVIN and QVIN signals into an
internal 6-bit digital representation for processing. The following pins
support the ADC module.