參數(shù)資料
型號: L6566ATR
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: 0.8 A POWER FACTOR CONTROLLER WITH POST REGULATOR, 300 kHz SWITCHING FREQ-MAX, PDSO16
封裝: LEAD FREE, SOP-16
文件頁數(shù): 15/51頁
文件大?。?/td> 646K
代理商: L6566ATR
Application information
L6566A
22/51
Note:
When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Thus one or more longer switching
cycles will be compensated by one or more shorter cycles and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.
If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is
smaller than the arming threshold for some reason (e.g. a heavy damping of drain
oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used),
MOSFET’s turn-on cannot be triggered. This case is identical to what happens at start-up:
at the end of the next oscillator cycle the MOSFET will be turned on, and a new switching
cycle will take place after skipping no more than one oscillator cycle.
The operation described so far does not consider the blanking time TBLANK after MOSFET’s
turn off, and actually TBLANK does not come into play as long as the following condition is
met:
Equation 3
where D is the MOSFET duty cycle. If this condition is not met, things do not change
substantially: the time during which MOSFET’s turn-on is inhibited is extended beyond Tosc
by a fraction of TBLANK. As a consequence, the maximum switching frequency will be a little
lower than the programmed value fosc and valley-skipping mode may take place slightly
earlier than expected. However this is quite unusual: setting fosc = 150 kHz, the
phenomenon can be observed at duty cycles higher than 60 %. See Section 5.11: OVP
for further implications of TBLANK.
If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an
internal pull-up keeps the ZCD pin close to 2 V during MOSFET's OFF-time to prevent noise
from false triggering the detection block. When this pull-up is active, the ZCD pin might not
be able to go below the triggering threshold, which would stop the converter. To allow auto-
restart operation, however ensuring minimum operating frequency in these conditions, the
oscillator frequency that retriggers MOSFET's turn-on is that of the external oscillator
divided by 128. Additionally, to prevent malfunction at converter's start-up, the pull-up is
disabled during the initial soft-start (see the relevant section). However, to ensure a correct
start-up, at the end of the soft-start phase the output voltage of the converter must meet the
condition:
Equation 4
where Ns is the turn number of the secondary winding, Naux the turn number of the
auxiliary winding and IZCD the maximum pull-up current (130 μA).
osc
BLANK
T
1
D
ZCD
1
Z I
R
Naux
Ns
Vout
>
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