參數(shù)資料
型號(hào): L6566ATR
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: 0.8 A POWER FACTOR CONTROLLER WITH POST REGULATOR, 300 kHz SWITCHING FREQ-MAX, PDSO16
封裝: LEAD FREE, SOP-16
文件頁(yè)數(shù): 35/51頁(yè)
文件大小: 646K
代理商: L6566ATR
Application information
L6566A
40/51
the base terminal are several ten kW) but this could distort the signal on the MULT pin of the
PFC chip and adversely affect the operation of the pre-regulator. CF needs to be quite a big
capacitor (in the
μF) to have small residual ripple superimposed on the dc level; as a rule-of-
thumb, use a time constant (RL + RH)CF at least 4-5 times the maximum line cycle period,
then fine tune if needed, considering also transient conditions such as mains missing
cycles.
If temperature effects are critical, the NPN Q can be replaced by a PNP-NPN pair arranged
as shown in Figure 26 on page 39 on the right-hand side; other sensing techniques can be
adopted anyway.
The voltage on the pin is clamped upwards at about 3.15 V; then, if the function is not used
the pin has to be connected to Vcc through a resistor (220 to 680 k
Ω).
5.13
Slope compensation
The pin MODE/SC (12), when not connected to VREF, provides a voltage ramp during
MOSFET's ON-time synchronous to that of the internal oscillator sawtooth, with 0.8 mA
minimum current capability. This ramp is intended for implementing additive slope
compensation on current sense. This is needed to avoid the sub-harmonic oscillation that
arises in all peak-current-mode-controlled converters working at fixed frequency in
continuous conduction mode with a duty cycle close to or exceeding 50 %.
Figure 27.
Slope compensation waveforms
The compensation will be realized by connecting a programming resistor between this pin
and the current sense input (pin 7, CS). The CS pin has to be connected to the sense
resistor with another resistor to make a summing node on the pin. Since no ramp is
delivered during MOSFET OFF-time (see Figure 27), no external component other than the
programming resistor is needed to ensure a clean operation at light loads.
Note:
The addition of the slope compensation ramp will reduce the available dynamics of the
current signal; thereby, the value of the sense resistor must be determined taking this into
account. Note also that the burst-mode threshold (in terms of power) will be slightly
changed.
If slope compensation is not required with FF operation, the pin shall be left floating.
Internal
oscillator
GD
(pin 4)
MODE/SC
(pin 12)
t
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