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參數(shù)資料
| 型號： | L6701TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.5 A SWITCHING REGULATOR, 110 kHz SWITCHING FREQ-MAX, PDSO36 |
| 封裝： | LEAD FREE, SSO-36 |
| 文件頁數(shù)： | 17/44頁 |
| 文件大?。?/td> | 627K |
| 代理商： | L6701TR |
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10 Output Voltage Positioning
L6701
24/44
Table 9.
Comparison between different load-line implementations.
10.3
Offset (Optional)
Positive offset can be added to the programmed reference by connecting a ROS resistor
between the REF_OUT and REF_IN pins. Referring to Figure 7, a constant current
(IOS=11.5A) is sourced from the REF_IN pin as soon as the device is enabled, so
programming a fixed voltage drop across ROS: this voltage is directly added to the programmed
reference giving the desired offset to the output voltage as follow:
Offset current is suddenly sourced from REF_IN pin as soon as the device implements Soft-
Start: to avoid having steps during soft-start, the introduction of COS (in parallel to ROS) is
required. The resulting time constant need to be negligible with respect to the soft-start time as
well as long enough to smooth the initial step. Typical values are in the range of few hundreds
of nF.
Offset function can be easily disabled simply setting ROS = 0.
Caution:
Offset automatically given by the DAC selection differs from the offset implemented through the
OFFSET pin: the built-in feature is trimmed in production and assures ±0.7% accuracy over
load and line variations.
10.4
Remote Voltage Sense
L6701 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any
additional external components. In this way, the output voltage programmed is regulated
between the remote buffer inputs compensating motherboard or connector losses. The device
senses the output voltage remotely through the pins FBR and FBG (FBR is for the regulated
voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors. Keeping the FBR and FBG traces parallel and
guarded by a power plane results in common mode coupling for any picked-up noise.
Fully-Differential LL
Non-Fully-Differential LL
Layout-insensitive BOM
Y
N
Time-Constant Matching
RD Design (given OCP th.)
RFB Design (given RLL)
RLL (given RD and RFB)
L
DCR
-------------
R
PH
C
PH
=
L
DCR
-------------
R
PH
C
PH
3
---------------------------
=
R
D
OCP
DCR
35
-------------
=
R
D
OCP
3
-------------
DCR
35
-------------
=
R
FB
R
LL
3
----------
R
D
DCR
-------------
=
R
FB
R
LL
R
D
DCR
-------------
=
R
LL
3
DCR
R
D
------------- RFB
=
R
LL
DCR
R
D
------------- RFB
=
V
OS
R
OS
I
OS
=
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