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L6712A L6712
Integrated power drivers reduce components count and interconnections between control functions and
drivers, reducing the board space.
Here below are listed the main points to focus on when starting a new layout and rules are suggested for
a correct implementation.
■ Power Connections.
These are the connections where switching and continuous current flows from the input supply towards
the load. The first priority when placing components has to be reserved to this power section, minimizing
the length of each connection as much as possible.
To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power
plane and anyway realized by wide and thick copper traces.
Figure 19. Power connections and related connections layout guidelines (same for both phases).
The critical components, i.e. the power transistors, must be located as close as possible, together and to
the controller. Considering that the "electrical" components reported in figure are composed by more than
one "physical" component, a ground plane or "star" grounding connection is suggested to minimize effects
due to multiple connections.
Figure 19a shows the details of the power connections involved and the current loops. The input capaci-
tance (CIN), or at least a portion of the total capacitance needed, has to be placed close to the power sec-
tion in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL
capacitors are required.
■ Power Connections Related.
Figure 19b shows some small signal components placement, and how and where to mix signal and power
ground planes. The distance from drivers and mosfet gates should be reduced as much as possible. Prop-
agation delay times as well as for the voltage spikes generated by the distributed inductance along the
copper traces are so minimized.
In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a con-
sequence, the higher are the voltage spikes corresponding to the gate PWM rising and falling signals.
Even if these spikes are clamped by inherent internal diodes, propagation delays, noise and potential
causes of instabilities are introduced jeopardizing good system behavior. One important consequence is
that the switching losses for the high side mosfet are significantly increased.
For this reason, it is suggested to have the device oriented with the driver side towards the mosfets and
the GATEx and PHASEx traces walking together toward the high side mosfet in order to minimize distance
(see
Figure 20). In addition, since the PHASEx pin is the return path for the high side driver, this pin must
be connected directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the
LS mosfets, the return path is the PGND pin: it can be connected directly to the power ground plane (if
VIN
LOAD
HS
Rgate
LS
Rgate
HGATEx
PHASEx
LGATEx
PGNDx
CIN
COUT
L
D
CBOOTx
VIN
LOAD
HS
LS
BOOTx
PHASEx
VCC
SGND
CIN
COUT
L
D
+VCC
CVCC
a. PCB power and ground planes areas
b. PCB small signal components placement