參數(shù)資料
型號: L6712Q
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: 2 A SWITCHING CONTROLLER, QCC36
封裝: 6 X 6 MM, 1 MM HEIGHT, VFQFPN-36
文件頁數(shù): 4/29頁
文件大?。?/td> 624K
代理商: L6712Q
L6712A L6712
12/29
circuitry reads the current during the time in which the low-side mosfet is on (OFF Time). During this time,
the reaction keeps the pin ISENx and PGNDSx at the same voltage while during the time in which the
reading circuitry is off, an internal clamp keeps these two pins at the same voltage sinking from the ISENx
pin the necessary current (Needed if low-side mosfet RdsON sense is implemented to avoid absolute max-
imum rating overcome on ISENx pin).
The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive
and negative current. This circuit reproduces the current flowing through the sensing element using a high
speed Track & Hold transconductance amplifier. In particular, it reads the current during the second half
of the OFF time reducing noise injection into the device due to the mosfet turn-on (See Figure 8-left). Track
time must be at least 200ns to make proper reading of the delivered current.
This circuit sources a constant 50
A current from the PGNDSx pin: it must be connected through the Rg
resistor to the ground side of the sensing element (See Figure 8-right). The two current reading circuitries
use this pin as a reference keeping the ISENx pin to this voltage.
The current that flows in the ISENx pin is then given by the following equation:
Where RSENSE is an external sense resistor or the RdsON of the low side mosfet and Rg is the transcon-
ductance resistor used between ISENx and PGNDSx pins toward the reading points; IPHASEx is the current
carried by the relative phase. The current information reproduced internally is represented by the second
term of the previous equation as follow:
Since the current is read in differential mode, also negative current information is kept; this allow the de-
vice to check for dangerous returning current between the two phases assuring the complete equalization
between the phase's currents. From the current information of each phase, information about the total cur-
rent delivered (IFB = IINFO1 +IINFO2) and the average current for each phase (IAVG = (IINFO1 +IINFO2)/2 ) is
taken. IINFOX is then compared to IAVG to give the correction to the PWM output in order to equalize the
current carried by the two phases.
Figure 8. Current reading timing (left) and circuit (right)
The transconductance resistor Rg can be designed in order to have current information of 25
A per phase
at full nominal load; the over current intervention threshold is set at 140% of the nominal (IINFOx = 35A).
According to the above relationship, the over current threshold (IOCPx) for each phase, which has to be
placed at 1/2 of the total delivered maximum current, results:
I
ISENx
50
A
R
SENSE
I
PHASEx
R
g
-------------------------------------------------
50
AI
INFOx
+
=
+
=
I
INFOx
R
SENSE
I
PHASEx
R
g
-------------------------------------------------
=
R
SE
NSE
Rg
50
A
IISENx
I P
HAS
E
Rg
LGATEx
ISENx
PGNDSx
ILS1
ILS2
Track & Hold
IFB
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