參數(shù)資料
型號(hào): L6716
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: DUAL SWITCHING CONTROLLER, 225 kHz SWITCHING FREQ-MAX, QCC48
封裝: 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFQFP-48
文件頁(yè)數(shù): 27/57頁(yè)
文件大小: 829K
代理商: L6716
L6716
Dynamic VID transitions
Doc ID 14521 Rev 3
33/57
15
Dynamic VID transitions
The device is able to manage dynamic VID code changes that allow output voltage
modification during normal device operation.
OVP and UVP signals are masked during every VID transition and they are re-activated
after the transition finishes with a 15 s (typ) delay to prevent from false triggering due to the
transition.
When changing dynamically the regulated voltage (D-VID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current ID-VID needs to
be delivered, especially when increasing the output regulated voltage and it must be
considered when setting the overcurrent threshold.
This current can be estimated using the following relationships:
where dVOUT is the selected DAC LSB (6.25 mV for VR11.1) and TVID is the time interval
between each LSB transition (externally driven).
Overcoming the OC threshold during the dynamic VID causes the device to enter the
constant current limitation slowing down the output voltage dV/dt also causing the failure in
the D-VID test.
In order to avoid this situation the device automatically increases the OCP threshold to
150% of the selected OCP threshold during every VID transition (adding an extra 15 s of
delay).
If the DVID (dynamic VID change) happens during low power state (PSI low), the device
turns on all the N phases in order to follow the DVID change reducing the over/under shoot
of the output voltage.
L6716 checks for VID code modifications (See Figure 17) on the rising edge of an internal
additional DVID-clock and waits for a confirmation on the following falling edge. Once the
new code is stable, on the next rising edge, the reference starts stepping up or down in LSB
increments every VID-clock cycle until the new VID code is reached. During the transition,
VID code changes are ignored; the device re-starts monitoring VID after the transition has
finished on the next rising edge available. VID-clock frequency (FDVID) is in the range of 1.8
MHz to assure compatibility with the specifications.
Note:
If the new VID code is more than 1 LSB different from the previous, the device will execute
the transition stepping the reference with the DVID-clock frequency FDVID until the new code
has reached: for this reason it is recommended to carefully control the VID change rate in
order to carefully control the slope of the output voltage.
I
DVID
C
OUT
dV
OUT
dT
VID
------------------
=
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