參數(shù)資料
型號: L6716
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: DUAL SWITCHING CONTROLLER, 225 kHz SWITCHING FREQ-MAX, QCC48
封裝: 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFQFP-48
文件頁數(shù): 48/57頁
文件大小: 829K
代理商: L6716
Layout guidelines
L6716
52/57
Doc ID 14521 Rev 3
24
Layout guidelines
Since the device manages control functions and high-current drivers, layout is one of the
most important things to consider when designing such high current applications. A good
layout solution can generate a benefit in lowering power dissipation on the power paths,
reducing radiation and a proper connection between signal and power ground can optimize
the performance of the control loops.
Two kind of critical components and connections have to be considered when layouting a
VRM based on L6716: power components and connections and small signal components
connections.
24.1
Power components and connections
These are the components and connections where switching and high continuous current
flows from the input to the load. The first priority when placing components has to be
reserved to this power section, minimizing the length of each connection and loop as much
as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections
must be a part of a power plane and anyway realized by wide and thick copper traces: loop
must be anyway minimized. The critical components, i.e. the power transistors, must be
close one to the other. The use of multi-layer printed circuit board is recommended.
Figure 30 shows the details of the power connections involved and the current loops. The
input capacitance (CIN), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be
connected near the HS drain.
Figure 30.
Power connections and related connections layout (same for all phases)
Note:
Boot capacitor extra charge. Systems that do not use Schottky diodes might show big
negative spikes on the phase pin. This spike can be limited as well as the positive spike but
has an additional consequence: it causes the bootstrap capacitor to be over-charged. This
extra-charge can cause, in the worst case condition of maximum input voltage and during
particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also
causing device failures. It is then suggested in this cases to limit this extra-charge by adding
a small resistor in series to the boot diode (one resistor can be enough for all the three
diodes if placed upstream the diode anode, see Figure 30) and by using standard and low-
capacitive diodes.
Use proper VIAs number when power traces have to move between different planes on the
PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the
L
CIN
VIN
UGATEx
PHASEx
LGATEx
PGND
LOAD
BOOTx
PHASEx
VCC
SGND
+Vcc
C
BOOT
L
CIN
VIN
LOAD
To limit C
BOOT
Extra-Charge
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