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| 型號： | L8575 |
| 英文描述： | Dual-Resistive,Low-Cost Subscriber Line Interface Circuit(SLIC) |
| 中文描述： | 雙電阻，低成本用戶線接口電路（SLIC） |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 633K |
| 代理商： | L8575 |
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L8575
Dual-Resistive, Low-Cost SLIC
Advance Data Sheet
March 1997
14
Lucent Technologies Inc.
Electrical Characteristics
(continued)
Serial Interface and Logic
The tables below summarize the parameter and timing requirements for logic inputs CLK, EN, DI, and DO.
Table 8. Logic Inputs (CLK, EN, and DI) and Outputs (DO)
1.
Unless otherwise specified, all logic voltages are referenced to DGND.
2.This parameter is not tested in production. It is guaranteed by design and device characterization.
Table 9. Timing Requirements for CLK, EN, DI, and DO
1.Unless otherwise specified, all times are measured from the 50% point of logic transitions.
2.This parameter is not tested in production. It is guaranteed by design and device characterization.
Parameter
1
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
I
OSS
C
OL
Min
2
0
—
Max
V
DDD
0.8
±
50
V
DDD
0.4
35
50
Unit
V
V
μ
A
V
V
mA
pF
High-level Input Voltage
Low-level Input Voltage
Input Bias Current (high and low)
High-level Output Voltage (I
OUT
= –100
μ
A)
Low-level Output Voltage (I
OUT
= 180
μ
A)
Output Short-circuit Current (V
OUT
= V
DDD
)
Output Load Capacitance
2
V
DDD
– 1.5
0
1
0
Parameter
1
Symbol
t
R
, t
F
C
IN
f
MAX
t
PCO
t
PCR
t
SDC
t
SDE
t
SEC
t
HDC
t
HEC
t
WCK
t
WEN
Min
0
—
—
0
0
150
150
150
50
50
400
800
Max
70
5
1.25
350
10
—
—
—
—
—
—
—
Unit
ns
pF
MHz
ns
μ
s
ns
ns
ns
ns
ns
ns
ns
Input Rise and Fall Time, CLK & EN (10% to 90%)
2
Maximum Input Capacitance
2
Maximum CLK Frequency (50% duty cycle)
Propagation Delay, CLK to DO
2
Propagation Delay, EN to RD Outputs
2
Minimum Setup Time from DI to CLK
2
Minimum Setup Time from DI to EN
2
Minimum Setup Time from EN to CLK
2
Minimum Hold Time from CLK to DI
2
Minimum Hold Time from EN to CLK
2
Minimum Pulse Width of CLK
Minimum Pulse Width of EN
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