參數(shù)資料
型號(hào)： L8575
英文描述： Dual-Resistive,Low-Cost Subscriber Line Interface Circuit(SLIC)
中文描述： 雙電阻，低成本用戶線接口電路（SLIC）
文件頁(yè)數(shù)： 21/36頁(yè)
文件大?。?/td> 633K
代理商： L8575
Advance Data Sheet
March 1997
L8575
Dual-Resistive, Low-Cost SLIC
Lucent Technologies Inc.
21
Applications
(continued)
On-Hook Transmission
In powerup mode, the L8575 SLIC provides a dc bias
of 5.6 mA. The 5.6 mA bias is also present under on-
hook conditions. The L8575 SLIC is able to support on-
hook transmission because of this bias. It is sufficiently
high to drive a 3.17 dBm signal into a 600
or 900
loop under open-circuit conditions. An internal current
source provides a dc bias of 112
μ
A. There is an inter-
nal current gain of 50; thus (50 * 112
μ
A) 5.6 mA flows
from battery through R
1
to PR, and 5.6 mA flows from
PT through R
2
to ground under on-hook conditions.
Self-Test
The L8575 SLIC offers a self-test capability. This is set
via logic inputs D1 and D0 in the serial input data
stream. In this mode, shown in Figure 6, the Ring cur-
rent drive amplifier is saturated to ground, and the Tip
amplifier is saturated to battery, which causes both the
ring-trip and loop closure detectors to indicate an off-
hook condition. In this operation mode, the ring relay
must not be active. The ring relay driver output in the
L8575 is at package nodes RDR (A&B). These relay
drivers are controlled by logic inputs D2 (A&B) in the
serial input data stream. See Table 14 for details.
12-3423(F).r2
Figure 6. Self-Test Mode Circuit
Serial Data Interface
A 4-wire serial interface (DI, DO, CLK, and EN) is used
to pass data from the control logic on the line card to
the L8575 SLIC, and to pass detector information from
L8575 SLIC to the control logic on the line card. When
enable input EN is high, data on input DI is clocked into
an 8-bit shift register on a high-to-low transition of the
clock input CLK.
Eight latches (four per channel) are provided to store
the data. Data is loaded into the eight latches from
input DI and the first 7 bits of the shift register on the
high-to-low transition of EN. When EN is low, a high-to-
low transition on CLK loads all of the detector informa-
tion (loop closure, fault zero voltage, and ring-trip from
the internal detector circuitry) into the 8-bit shift regis-
ter. When EN is high, data in the 8-bit shift register is
clocked out on output DO on the high-to-low transition
of CLK.
Two latch outputs per channel drive relay drivers. The
drivers are included on the L8575 SLIC. These are the
relay drivers whose outputs are at external package
nodes RDR (A&B) and RDT (A&B). The remaining two
latch output power channels are internal control sig-
nals. These are logic data bits D0 (A&B) and D1 (A&B).
These bits input to a combinational logic circuit that
controls the operational state of each channel and also
controls the state of the third relay driver. The third
relay driver’s output is at external package node RDD
(A&B). Refer to the Truth Table (see Table 15) for more
details.
Note that up to 16 channels may be daisy-chained
together. The DO lead of package 1 (channels 1 and 2)
may be tied to the DI lead of package 2 (channels 3
and 4), etc. All EN and CLK should also be tied
together in this mode.
The L8575 SLIC device has an internal reset which
guarantees that all relay drivers power up in the off-
state when 5 V (V
CCD
and V
CCA
) is applied to the
device. This reset operates properly only if input EN
is held high (within 0.5 V of V
CCD
)
when the 5 V is
applied.
An external pull-up resistor from the EN bus to
V
CCD
satisfies this requirement, provided that the logic-
driving EN does not pull the EN bus low during pow-
erup.
+
–
LCA/B
+
–
RTA/B
PR
PTP
RTN
200 k
200 k
100 k
1.4 k
R
1.0 M
0.1
μ
F
1.0 M
8.25 M
300
V
RING
V
BAT
PT
T
1.4 k
100 k
300 k
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