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參數(shù)資料
| 型號(hào)： | LAN83C180 |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10/100 FAST ETHERNET PHY TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 166K |
| 代理商： | LAN83C180 |
SMSC DS – LAN83C180
Page 16
Rev. 08/24/2001
Reg 24 - LAN83C180 Specific Register
BIT
15:14
13
BIT NAME
Test Access
LED Control
DESCRIPTION
DEFAULT
00b
0
TYPE
R/W
R/W
Reserved SMSC test access only
0 = COLST active on collision
1 = COLST active on Sync/polarity
0 = MINT output active low
1 = MINT output active high
Disable 10BASE-T autopolarity correction
0 = SQE generation (normal operation)
1 = No SQE generation
0 = In case of jabber the 10BASE-T will cut the
frame (normal operation)
1 = Jabber function disable
Disable loopback of TX to RX in 10BASE-T half
duplex
Force reception regardless of link
Force transmission regardless of link
CRS behavior in FDX –
0 = CRS is active during transmission only
1= CRS active during reception only
0 = Normal operation
1 = Disable the MD preamble function
0 = Normal operation
1 = Bypass the aligner function
0 = Normal operation
1 = Bypass the 4B5B encoder function
0 = Normal operation
1 = Bypass the 4B5B scrambler function
Disconnect mechanism enable
12
MINT POL
0
R/W
11
10
Pol Dis
SQE Disable
0
0
R/W
R/W
9
JAB Disable
0
R/W
8
Loop 10
0
R/W
7
6
5
Force RX
Force TX
CRS_CTL
0
0
0
R/W
R/W
R/W
4
MF
0
R/W
3
Byp ALIGN
0
R/W
2
Byp ENC
0
R/W
1
Byp SCR
0
R/W
0
DISCEN
0 – DTE
1 – RPT
Reg 25 - ANEG Status
BIT
15
14
13
12:8
7
BIT NAME
Reserved
Reserved
Pol
PA
Aneg complete
DESCRIPTION
DEFAULT
0
0
0
PA<4:0>
0
TYPE
R/W
R/W
RO
RO
RO
Test mode only - do not set high
Test mode only - do not set high
10BASE-T polarity sense
PHY address
0 = Aneg completed
1 = Aneg did not complete (same as 1.5)
ANEG result - duplex operation
0 = HDX, 1 = FDX
ANEG result - speed of operation
0 = 10, 1 = 100
1 = abilities matched
ANEG state machine current state
6
Duplex
0
RO
5
Speed
0
RO
4
Ability mtc
ANEG state
0
0
RO
RO
0:3
Reg 26 - Symbol Error Counter
BIT
15:0
BIT NAME
RX_ERR
counter
DESCRIPTION
DEFAULT
0
TYPE
RO
SC
Number of RX_ERR events since last read –
clears either in change of speed or read of this
reg.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LAN83C180_01 | 制造商:SMSC 制造商全稱:SMSC 功能描述:10/100 Fast Ethernet PHY Transceiver |
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| LAN83C183 | 制造商:SMSC 制造商全稱:SMSC 功能描述:FAST ETHERNET PHYSICAL LAYER DEVICE |
| LAN83C183-JD | 制造商:SMSC 制造商全稱:SMSC 功能描述:FAST ETHERNET PHYSICAL LAYER DEVICE |
| LAN83C185 | 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver |
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