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參數(shù)資料
| 型號(hào)： | LAN83C180 |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10/100 FAST ETHERNET PHY TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 5/22頁(yè) |
| 文件大小： | 166K |
| 代理商： | LAN83C180 |
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SMSC DS – LAN83C180
Page 5
Rev. 08/24/2001
DESCRIPTION OF PIN FUNCTIONS
PIN #
NAME
TYPE
DESCRIPTION
MD INTERFACE
Diff. Input
Diff. Input
Diff. Output
Diff. Output
Input
Input
Input
/
Output
19
18
25
26
33
34
13
RXIN
RXIP
TXON
TXOP
TXREF10
TXREF100
nRESET
Differential receive pair from magnetics (-)
Differential receive pair from magnetics (+)
100 Differential transmit pair to magnetics (-)
100 Differential transmit pair to magnetics (+)
10BASE-T transmitter current setting pin
100BASE-TX transmitter current setting pin
Active low, power-on reset output and external reset
input.
41
XTAL1
Input
25MHz crystal input.
This signal should be pulled
high when using REFCLK.
25MHz crystal input.
This signal should be left
unconnected when using REFCLK.
MII INTERFACE
Input
Management interface clock (up to 2.5MHz)
Input/
OUTPUT
Output
Receive clock (2.5MHz for 10, 25MHz for 100)
Output
Receive data MII interface
40
XTAL2
Input
46
45
MDC
MDIO
Management data
52
RX_CLK
55,56,57,5
8
51
59
1
60,61,62,6
3
3
64
50
49
RXD0,RXD1,RXD2,
RXD3
RX_DV
RX_ER
TX_CLK
TXD0,TXD1,TXD2,T
XD3
TX_EN
TX_ER
CRS
COL
Output
Output
Output
Input
Receive data valid. Active high
Receive error. Active high. (RXD4 in symbol mode)
Transmit clock (2.5MHz for 10, 25MHz for 100)
Transmit Data MII interface
Input
Input
Output
Output
MISCELLANEOUS
Input
Transmit Enable. Active high
Transmit Error. Active high. (TXD4 in symbol mode)
Carrier sense signal. Active high
Collision signal. Active high
43
REFCLK
Reference clock.
This signal should be pulled high
when using crystal
.
Auto Negotiation enable. Active high
Receive enable. Active high
Repeater enable. Active high
PHY address
22
48
21
ANEN
RXEN
RPTR
PA0,PA1,
PA2,PA3,PA4
Input
Input
Input
Input
31,30,29,1
6,12
MISCELLANEOUS/LED
Input/
OUTPUT
high. Active low. Input when nRESET is low. High
input means the LAN83C180 advertises full duplex
capability
Input
Speed (10/100) LED status indication when
nRESET high. High for 100Mb/s mode. Input when
nRESET is low. Low input will cause the
LAN83C180 to advertise 100Mb/s capability.
Input
Interrupt configuration. MINT on pin 8 when High,
on pin 7 when Low.
Output
Receive/Transmit activity LED status indication
(Active Low) if ICFG = 1. If ICFG = 0, output is
MINT and activity is indicated on the LNKST output.
4
FDST
Full duplex LED status indication when nRESET
6
SPDST
23
ICFG
7
ACTST/
MINT
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