參數(shù)資料
型號(hào): LC5256MC-4F256C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類(lèi): PLD
英文描述: 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述: EE PLD, 4.8 ns, PBGA256
封裝: FPBGA-256
文件頁(yè)數(shù): 33/92頁(yè)
文件大?。?/td> 378K
代理商: LC5256MC-4F256C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
33
Registered Delays
t
S
D-Register Setup
Time, Global Clock
D-Register Setup
Time, PT Clock
D-Register Hold
Time
Register Clock to
OSA Time
Clock Enable Setup
Time
Clock Enable Hold
Time
D-Input Register
Setup Time, Global
Clock
D-Input Register
Setup Time, PT
Clock
D-Input Register
Hold Time, Global
Clock
D-Input Register
Hold Time, PT
Clock
0.28
0.31
0.35
0.55
0.52
ns
t
S_PT
-0.13
-0.11
-0.10
-0.10
-0.07
ns
t
H
1.90
2.56
2.50
2.40
4.00
ns
t
COi
0.72
1.03
0.68
0.93
1.50
ns
t
CESi
1.07
1.20
1.33
1.33
2.00
ns
t
CEHi
0.00
0.00
0.00
0.00
0.00
ns
t
SIR
0.66
0.20
0.53
0.12
0.08
ns
t
SIR_PT
0.42
0.37
0.34
0.34
0.22
ns
t
HIR
0.84
1.31
1.01
1.41
2.91
ns
t
HIR_PT
0.00
0.00
0.00
0.00
0.00
ns
Latched Delays
t
SL
Latch Setup Time,
Global Clock
Latch Setup Time,
PT Clock
Latch Hold Time
Latch Gate to OSA
Time
Propagation Delay
through Latch to
OSA Transparent
0.18
0.00
0.00
0.00
0.00
ns
t
SL_PT
0.18
0.00
0.00
0.00
0.34
ns
t
HL
-0.06
0.00
0.00
0.00
-0.03
ns
t
GOi
0.07
0.08
0.08
0.08
0.13
ns
t
PDLi
0.52
0.58
0.65
0.65
0.97
ns
Reset and Set Delays
t
SRi
Asynchronous
Reset or Set to OSA
Delay
Asynchronous
Reset or Set
Recovery
0.23
0.26
0.29
0.29
0.43
ns
t
SRR
0.42
0.47
0.53
0.55
0.79
ns
eXtended Function Routing Delays
Delay through SRP
when Implementing
Memory Functions
t
ROUTEMF
2.00
2.25
2.51
2.61
3.76
ns
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
Base
Parameter
-4
-45
-5
-52
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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