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參數(shù)資料
| 型號(hào)： | LC5256MC-4F256C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| 中文描述： | EE PLD, 4.8 ns, PBGA256 |
| 封裝： | FPBGA-256 |
| 文件頁(yè)數(shù)： | 49/92頁(yè) |
| 文件大小： | 378K |
| 代理商： | LC5256MC-4F256C |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
49
Signal Descriptions
Signal Names
Descriptions
TMS
Input – This pin is the Test Mode Select input, which is used to control the IEEE 1149.1
state machine.
Input – This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state
machine.
Input – This pin is the IEEE 1149.1 Test Data in pin, used to load data.
Output – This pin is the IEEE 1149.1 Test Data out pin used to shift data out.
Input – Test Output Enable pin. TOE tristates all I/O pins when driven low.
Input – Global output enable inputs.
Input – This pin resets all the registers in the device. The global polarity (active high or
active low) for this pin is selectable on a global basis.
Input/Output – These are the general purpose I/O used by the logic array.
y
is the MFB
reference (alpha) and z is the macrocell reference (numeric)
y: A-X (768 macrocells)
y: A-P (512 macrocells)
y: A-H (256 macrocells)
z: 0-31
GND – Ground
No connect
V
CC
– The power supply pins for core logic.
V
CC
– The power supply pins for I/O banks 0, 1, 2, and 3.
Input – This pin de
fi
nes the reference voltage for I/O banks 0, 1, 2, and 3.
Input – Global clock/clock enable inputs (see Figure 14 for differential pairing).
Output – Optional clock output from PLL 0 and 1.
Input – Optional input resets the M divider in PLL 0 and 1.
Input – Optional feedback input for PLL 0 and 1.
GND – Ground for PLLs.
V
CC
– The power supply pin for PLLs.
V
CC
– The power supply for the IEEE 1149.1 interface.
I/O – sysCONFIG data pins, bit
x
.
Input – sysCONFIG interface chip select. Drive low to select sysCONFIG interface.
Input – De
fi
nes SRAM con
fi
guration mode. Low: sysCONFIG port, high: E
2
CMOS or
IEEE 1149.1 TAP.
Input – Controls the programming of SRAM. Hold high for normal operation. Toggle low
to reload SRAM from E
2
memory.
Input – Clock for sysCONFIG interface. Reads and writes occur on the rising edge of
the clock.
Input – Drive high to perform reads from the sysCONFIG interface.
I/O – Indicates status of con
fi
guration. Can be driven low to inhibit con
fi
guration.
Output (open drain) – Indicates status of con
fi
guration.
1. These inputs should not toggle during power up for proper power-up con
fi
guration.
TCK
TDI
TDO
TOE
GOE0, GOE1
RESET
yzz
GND
NC
V
CC
V
CCO0,
V
CCO1,
V
CCO2,
V
CCO3
V
REF0,
V
REF1,
V
REF2,
V
REF3
GCLK0, GCLK1, GCLK2, GCLK3
CLK_OUT0, CLK_OUT1
PLL_RST0, PLL_RST1
PLL_FBK0, PLL_FBK1
GNDP
V
CCP
V
CCJ
DATA
x
CSB
CFG0
PROGRAMB
CCLK
1
READ
1
INITB
DONE
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相關(guān)代理商/技術(shù)參數(shù) |
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| LC5256MC-4F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5256MC-4F484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5256MC-4F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5256MC-4F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5256MC-4F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
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