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    參數(shù)資料
    

    


    


    
型號：
LC5512MC-75F484I

    

    
廠商：
Lattice Semiconductor Corporation

    

    
文件頁數(shù)：
11/99頁

    

    
文件大?。?/td>
0K

    

    
描述：
IC XPLD 512MC 7.5NS 484FPBGA

    

    
標準包裝：
60

    

    
系列：
ispXPLD® 5000MC

    

    
可編程類型：
系統(tǒng)內(nèi)可編程
    		

    

    
最大延遲時間 tpd(1)：
7.5ns
    		

    

    
電壓電源 - 內(nèi)部：
1.65 V ~ 1.95 V
    		

    

    
邏輯元件/邏輯塊數(shù)目：
16
    		

    

    
宏單元數(shù)：
512
    		

    

    
輸入/輸出數(shù)：
253
    		

    

    
工作溫度：
-40°C ~ 105°C
    		

    

    
安裝類型：
表面貼裝
    		

    

    
封裝/外殼：
484-BBGA
    		

    

    
供應(yīng)商設(shè)備封裝：
484-FPBGA（23x23）
    		

    

    
包裝：
托盤
    		

    

    

    

	
    
    
    

    
    
	
    Lattice Semiconductor
    ispXPLD 5000MX Family Data Sheet
    15
    Clock Distribution
    The ispXPLD 5000MX family has four dedicated clock input pins: GCLK0-GCLK3. GLCK0 and GCLK3 can be
    routed through a PLL circuit or routed directly to the internal clock nets. The internal clock nets (CLK0-CLK3) are
    directly related to the dedicated clock pins (see Secondary Clock Divider exception when using the sysCLOCK cir-
    cuit). These feed the registers in the MFBs. Note at each register there is the option of inverting the clock if
    required. Figure 14 shows the clock distribution network.
    Figure 14. Clock Distribution Network
    sysCLOCK PLL
    The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset and feedback
    signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener-
    ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are de-
    skewed either at the board level or the device level.
    The ispXPLD 5000MX devices provide two PLL circuits. PLL0 receives its clock inputs from GCLK 0 and provides
    outputs to CLK 0 (CLK 1 when using the secondary clock). PLL1 operates with signals from GCLK 3 and CLK 3
    (CLK 2 when using the secondary clock). The optional outputs CLK_OUT can be routed to an I/O pin. The optional
    PLL_LOCK output is routed into the GRP. The optional input PLL_RST can be routed either from the GRP or
    directly from an I/O pin. The optional PLL_FBK into can be routed directly from a pin. Figure 15 shows the ispXPLD
    5000MX PLL block diagram. Figure 16 shows the connection of optional inputs and outputs.
    sysCLOCK PLLs
    Global Clock Routing
    Clock Net
    PLL0
    CLK_OUT0
    SEC_OUT0
    VREF0
    CLK0
    CLK1
    GCLK0
    GCLK1
    I/O/CLK_OUT0
    Clock Net
    PLL1
    CLK_OUT1
    SEC_OUT1
    CLK3
    CLK2
    GCLK3
    GCLK2
    I/O/CLK_OUT1
    Clock Net
    To Macrocells
    VREF1
    VREF3
    VREF2
    SELECT
    DEVICES
    DISCONTINUED
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
LC5512MC-75F672C
 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family

    

    
LC5512MC-75F672I
 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family

    

    
LC5512MC-75FN208C
 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family

    

    
LC5512MC-75FN208I
 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family

    

    
LC5512MC-75FN256C
功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
    
    
    
	
    	
    
    
     
     
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