參數(shù)資料
型號: LC5512MV-75F484C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 26/99頁
文件大?。?/td> 0K
描述: IC XPLD 512MC 7.5NS 484FPBGA
標(biāo)準(zhǔn)包裝: 60
系列: ispXPLD® 5000MV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 16
宏單元數(shù): 512
輸入/輸出數(shù): 253
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 484-BBGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
28
sysIO Differential DC Electrical Characteristics
Over Recommended Operating Conditions
Figure 19. LVPECL Driver with Three Resistor Pack
Parameter
Description
Test Conditions
Min.
Typ.
Max.
LVDS
VINP
Input Voltage
0V
2.4V
VTHD
Differential Input Threshold
0.2 VCM 1.8V
+/-100mV
IIN
Input Current
Power On
+/-10uA
VOH
Output High Voltage for VOP or VOM
RT = 100 Ohm
1.38V
1.60V
VOL
Output Low Voltage for VOP or VOM
RT = 100 Ohm
0.9V
1.03V
VOD
Output Voltage Differential
(VOP - VOM), RT = 100 Ohm
250mV
350mV
450mV
V
OD
Change in VOD Between High and Low
50mV
VOS
Output Voltage Offset
(VOP - VOM)/2, RT = 100 Ohm
1.125V
1.20V
1.375V
V
OS
Change in VOS Between H and L
50mV
IOSD
Output Short Circuit Current
VOD = 0V Driver outputs
shorted
——
24mA
LVPECL
1
DC
Parameter
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
VCCO
3.0
3.3
3.6
V
VIH
Input Voltage High
1.49
2.72
1.49
2.72
1.49
2.72
V
VIL
Input Voltage Low
0.86
2.125
0.86
2.125
0.86
2.125
V
VOH
Output Voltage High
1.7
2.11
1.92
2.28
2.03
2.41
V
VOL
Output Voltage Low
0.96
1.27
1.06
1.43
1.3
1.57
V
VDIFF
2
Differential Input voltage
0.3
0.3
0.3
V
1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 19).
The VOH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.
2. Valid for 0.2 VCM 1.8V
Zo
Rs
R
D
A
Rs
to LVPECL
differential
receiver
1/4 of Bourns P/N
CAT 16-PC4F12
ispXPLD Emulated
LVPECL Buffer
R
T
0
1
=
SELECT
DEVICES
DISCONTINUED
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