參數(shù)資料
型號： LC5512MV-75F484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 99/99頁
文件大小： 0K
描述： IC XPLD 512MC 7.5NS 484FPBGA
標(biāo)準(zhǔn)包裝： 60
系列： ispXPLD® 5000MV
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 512
輸入/輸出數(shù)： 253
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
包裝： 托盤
Lattice Semiconductor
ispGDX2V/B/C Family Data Sheet
95
Revision History
Date
Version
Change Summary
—
Previous Lattice releases.
December 2003
07
Added ispXPLD 5768MX information (supply current, timings, power consumption, power estima-
tion coefficients, memory coefficients, logic signal connections, ordering part numbers).
Updated ispXPLD 5000MX timing numbers (version v.1.7).
Added lead-free package designator.
Removed ispXPLD 5000MC industrial temperature grade ordering part numbers.
January 2004
08
Lead-free package release for the ispXPLD 5000MC and 5000MV devices.
Timing model parameter tCOi correction - Maximum specification instead of Minimum (no
changes in the timing numbers).
March 2004
08.1
Updated the MFB Cascade Chain table for the ispXPLD 5256MX device.
May 2004
09
Updated the ispXPLD 5000MX timig numbers (version v.1.8)
ispXPLD 5256MC, 5512MC and 51024MC industrial temperature grade devices release
Updated typical supply current data and condition.
ispXPLD 5256MX 256-fpBGA logic signal connection tables: Removed internal signal description
for ball H5 and G14.
August 2004
10
Added footnote "1, page 49. These inputs should not toggle during power up for proper power-up
configuration." to CCLK and READ.
Added ispXPLD 5768MC Industrial grade OPNs (Conventional and Lead-Free).
October 2004
10.1
Figure 19, LVPECL Driver with Three Resistor Pack has been updated (ispXPLD LVPECL Buffer
changed to ispXPLD Emulated LVPECL Buffer)
November 2004
11
Added ispXPLD 5000MB (2.5V) Lead-Free Ordering Part Numbers.
December 2004
11.1
Pin name RESETB has been updated to RESET.
March 2005
12
208-PQFP Lead-free package release for the ispXPLD 5512MV/B/C devices.
April 2005
12.1
Page 23, clarification of footnote regarding IDK specification.
March 2006
12.2
Signal description for RESET has been updated.
April 2009
12.3
Ordering Information section has been updated to describe alternate LC5768MB/MV top side
marking format.
February 2010
12.4
References to "system gates" changed to "functional gates."
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5512MV-75F484I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5512MV-75F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75FN208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75FN208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
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