參數(shù)資料
型號(hào)： LC5512MV-75F484C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 6/99頁
文件大?。?/td> 0K
描述： IC XPLD 512MC 7.5NS 484FPBGA
標(biāo)準(zhǔn)包裝： 60
系列： ispXPLD® 5000MV
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 512
輸入/輸出數(shù)： 253
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 484-BBGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
包裝： 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
10
True Dual-Port SRAM Mode
In Dual-Port SRAM Mode the multi-function array is configured as a dual port SRAM. In this mode two independent
read/write ports access the same 8,192-bits of memory. Data widths of 1, 2, 4, 8, and 16 are supported by the
MFB. Figure 9 shows the block diagram of the dual port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Resets are asynchronous. All inputs on the same port share the same
clock, clock enable, and reset selections. All outputs on the same port share the same clock, clock enable, and
reset selections. Selections may be made independently between both inputs and outputs and ports. Table 5
shows the possible sources for the clock, clock enable and initialization signals for the various registers.
Figure 9. Dual-Port SRAM Block Diagram
Table 5. Register Clock, Clock Enable, and Reset in Dual-Port SRAM Mode
Register
Input
Source
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Clock
CLKA (CLKB) or one of the global clocks (CLK0 - CLK3). The selected sig-
nal can be inverted if desired.
Clock Enable
CENA (CENB) or one of the global clocks (CLK1 - CLK 2). The selected sig-
nal can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RSTA (RSTB).
RSTA (RSTB) can be inverted is desired.
‘
Read/Write Address
(ADA[0:8-12])
Clock A (CLKA)
Write/Read A (WRA)
Reset A (RSTA)
68 Inputs
From
Routing
Dual
Port
SRAM
Array
PORT A
PORT B
Similar signals
as PORT A:
ADB[0:8-12], RSTB,
CLKB, CENB, WRB,
CSB[0,1], DIB[0:0,1,3,7,15]
Write Data
(DIA[0:0,1,3,7,15])
Chip Sel A (CSA [0:1])
Clk En A (CENA)
RESET
CLK0
CLK3
CLK1
CLK2
RD Data A
(DOA[0:0-15])
RD Data B
(DOB[0:0-15])
SELECT
DEVICES
DISCONTINUED
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5512MV-75F484I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5512MV-75F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75FN208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75FN208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
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