參數(shù)資料
型號: LC5768MC-5F484C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述: EE PLD, 6 ns, PBGA484
封裝: FPBGA-484
文件頁數(shù): 12/92頁
文件大小: 378K
代理商: LC5768MC-5F484C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
12
Single-Port SRAM Mode
In Single-Port SRAM Mode the multi-function array is con
fi
gured as a single-port SRAM. In this mode one ports
accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 11 shows
the block diagram of the single-port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Reset is asynchronous. All signals share a common clock, clock
enable, and reset. Table 7 shows the possible sources for the clock, clock enable and reset signals.
Figure 11. Single-Port SRAM Block Diagram
Table 7. Register Clock, Clock Enable, and Reset in Single-Port SRAM Mode
Register
Input
Source
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Clock
CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can
be inverted if required.
CEN or one of the global clocks (CLK1 - CLK 2). Each of these signals can
be inverted if required.
Created by the logical OR of the global reset signal and RST. RST is routed
by the multifunction array from GRP, with inversion if desired.
Clock Enable
Reset
68 Inputs
from
Routing
RESET
CLK0
CLK1
CLK2
16,384-Bit
SRAM
Array
Clock
(CLK)
Read/Write Address
(AD[0-8:13])
Write/Read
(WR)
Chip Select
(CS0,1)
Reset
(RST)
Clk Enable
(CEN)
Write Data
(DI[0-0,1,3,7,15,31])
Read Data
(DO[0-0,31])
相關(guān)PDF資料
PDF描述
LC5768MC-75F256C 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5768MC-75F484C 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC801 SILICON GATE ENHANCEMENT MODE RF POWER LDMOS TRANSISTOR
LC821 SILICON GATE ENHANCEMENT MODE RF POWER LDMOS TRANSISTOR
LCAS6-10-L VI CHIP Evaluation Board
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5768MC-5F484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5768MC-5F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5768MC-5F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5768MC-5FN208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5768MC-5FN208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family