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參數(shù)資料
| 型號： | LC5768MC-5F484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| 中文描述： | EE PLD, 6 ns, PBGA484 |
| 封裝： | FPBGA-484 |
| 文件頁數(shù)： | 43/92頁 |
| 文件大小： | 378K |
| 代理商： | LC5768MC-5F484C |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
43
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
t
PWH
t
PWL
t
R
, t
F
t
INSTB
f
MDIVIN
f
MDIVOUT
f
NDIVIN
f
NDIVOUT
f
VDIVIN
f
VDIVOUT
t
OUTDUTY
Parameter
Conditions
Min
1.2
1.2
—
—
10
10
10
10
100
10
40
Max
—
—
3.0
+/- 250
320
320
320
320
400
320
60
Units
ns
ns
ns
ps
MHz
MHz
MHz
MHz
MHz
MHz
%
Input clock, high time
Input clock, low time
Input Clock, rise and fall time
Input clock stability, cycle to cycle (peak)
M Divider input, frequency range
M Divider output, frequency range
N Divider input, frequency range
N Divider output, frequency range
V Divider input, frequency range
V Divider output, frequency range
Output clock, duty cycle
80% to 80%
20% to 20%
20% to 80%
t
JIT(CC)
Output clock, cycle to cycle jitter (peak)
Clean reference.
10 MHz < f
MDIVOUT
< 20 MHz or
100MHz < f
VDIVIN
< 160 MHz
1
Clean reference.
20 MHz < f
MDIVOUT
< 320 MHz and
160MHz < f
VDIVIN
< 320 MHz
1
Clean reference.
10 MHz < f
MDIVOUT
< 20 MHz or
100MHz < f
VDIVIN
< 160 MHz
1
Clean reference.
20 MHz < f
MDIVOUT
< 320 MHz and
160MHz < f
VDIVIN
< 320 MHz
1
Internal feedback
External feedback
—
+/- 250
ps
—
+/- 150
ps
T
JIT(PERIOD)
2
Output clock, period jitter (peak)
—
+/- 300
ps
—
+/- 150
ps
t
CLK_OUT_DLY
t
PHASE
t
LOCK
t
PLL_DELAY
t
RANGE
t
PLL_RSTW
t
CLK_IN
t
PLL_SEC_DELAY
Secondary PLL output delay (t
PLL_DELAY
)
1. This condition assures that the output phase jitter will remain within speci
fi
cation.
2. Accumulated jitter measured over 10,000 waveform samples.
3. Internal timing for reference only.
Input clock to CLK_OUT delay
Input clock to external feedback delta
Time to acquire phase lock after input stable
Delay increment (Lead/Lag)
Total output delay range (lead/lag)
Minimum reset pulse width
Global clock input delay
—
—
—
3.0
600
25
ns
ps
us
ps
ns
ns
ns
ns
Typical = +/- 250ps
+/- 120 +/- 550
+/- 0.84 +/- 3.85
—
—
—
1.8
1.0
1.5
3
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