參數(shù)資料
型號(hào)： LC72135M
元件分類(lèi)： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封裝： MFP-20
文件頁(yè)數(shù)： 4/24頁(yè)
文件大?。?/td> 300K
代理商： LC72135M
Continued from preceding page.
No. 5175-12/24
LC72135M
No.
Control block/data
Functions
Related data
I/O port specification data
Specifies the I/O direction for the bidirectional pin IO2.
IOC2
Data: 0 = input mode, 1 = output mode
Output port data
Data that determines the output from the BO1 to BO4, and IO2 output ports
BO1 to BO4, IO2
Data: 0 = open, 1 = low
The data = 0 (open) state is selected after the power-on reset.
DO pin control data
Data that determines the DO pin output
DOC0, DOC1, DOC2
The open state is selected after the power-on reset.
Note: 1. end-UC: Check for IF counter measurement completion
x. When end-UC is set and the IF counter is started (i.e., when CTE is changed
from zero to one), the DO pin automatically goes to the open state.
When the IF counter measurement completes, the DO pin goes low to indicate
the measurement completion state.
z Depending on serial data I/O (CE: high) the DO pin goes to the open state.
2. Goes to the open state if the LCTR/I1 pin is set to the AM-IF counter function
(L/I1 = 1).
3. Goes to the open state if the I/O pin is specified to be an output port.
Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE
high) will be open, regardless of the state of the DO control data (DOC0 to DOC2).
Also, the DO pin during a data output period (an OUT mode period with CE high)
will output the contents of the internal DO serial data in synchronization with the
CL pin signal, regardless of the state of the DO control data (DOC0 to DOC2).
Unlock detection data
Selects the phase error (E) detection width for checking PLL lock.
UL0, UL1
A phase error in excess of the specified detection width is seen as an unlocked state.
Note: In the unlocked state the DO pin goes low and the UL bit in the serial data
becomes zero.
Phase comparator
Controls the phase comparator dead zone.
control data
DZ0, DZ1
Dead zone widths: DZA < DZB < DZC < DZD
Clock time base
Setting TBC to one causes an 8 Hz, 40% duty clock time base signal to be output
TBC
from the BO1 pin. (BO1 data is invalid in this mode.)
Charge pump control data
Forcibly controls the charge pump output.
DLC
Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO
oscillator stopping, deadlock can be cleared by forcing the charge pump output to
low and setting Vtune to VCC. (This is the deadlock clearing circuit.)
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(7)
(8)
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UL0, UL1,
CTE,
IOC2
DOC0,
DOC1,
DOC2
BO1
IOC2
DOC2
DOC1
DOC0
DO pin state
0
Open
0
1
Low when the unlock state is detected
0
1
0
end-UC*1
0
1
Open
1
0
Open
1
0
1
The LCTR/I1 pin state*2
1
0
The IO2 pin state*3
1
Open
UL1
UL0
E detection width
Detector output
0
Stopped
Open
0
1
0
E is output directly
1
0
±0.55 s
E is extended by 1 to 2 ms
1
±1.11 s
E is extended by 1 to 2 ms
DZ1
DZ0
Dead zone mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
DLC
Charge pump output
0
Normal operation
1
Forced low
Continued on next page.
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相關(guān)PDF資料
PDF描述
LC72136NM PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72140M PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24
LC72140 PLL FREQUENCY SYNTHESIZER, 160 MHz, PDIP24
LC72146 PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP24
LC72146V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC72135MA-AE 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
LC72135MA-Q-AE 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Tape and Reel 制造商:ON Semiconductor 功能描述:REEL / PLL FREQUENCY SYNTHESIZER
LC72135M-Q-TLM-E 制造商:SANYO Semiconductor Co Ltd 功能描述:
LC72136 制造商:SANYO 制造商全稱(chēng):Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning
LC72136M 制造商:SANYO 制造商全稱(chēng):Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning
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