參數(shù)資料
型號: LC72135M
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封裝: MFP-20
文件頁數(shù): 5/24頁
文件大小: 300K
代理商: LC72135M
Continued from preceding page.
3. DO Output Data (Serial Data Output)
OUT Mode
4. DO Output Data
No. 5175-13/24
LC72135M
No.
Control block/data
Functions
Related data
This data should be set to 1 during normal operation.
IF counter control data
Note that if this value is set to zero the system enters input sensitivity degradation mode,
(11)
IFS
and the sensitivity is reduced to 10 to 30 mV rms.
* See the “IF Counter Operation” item for details.
LSI test data
TEST0
(12)
LSI test data
TEST1
These values must all be set to 0.
TEST 0 to 2
TEST2
These test data are set to 0 automatically after the power-on reset.
(13)
DNC
Don’t care. This data must be set to 0.
No.
Control block/data
Functions
Related data
I/O port data
Latched from the pin states of the LCTR/I1 input port (L/I1 bit is set to 0)
I2, I1
and the IO2 I/O port.
These values follow the pin states regardless of the input or output setting.
Data is latched when the data output mode is entered.
I1
← LCTR/I1 pin state
High: 1
I2
← IO2 pin state
Low: 0
PLL unlock data
Latched from the state of the unlock detection circuit.
UL
← 0: Unlocked
UL
← 1: Locked or detection stopped mode
IF counter binary data
Latched from the value of the IF counter (20-bit binary counter).
C19 to C0
C19
← MSB of the binary counter
C0
← LSB of the binary counter
(1)
(2)
(3)
L/I1
IOC2
UL0,
UL1
CTE,
GT0,
GT1
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