參數(shù)資料
型號: LC72146
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP24
封裝: SDIP-24
文件頁數(shù): 5/22頁
文件大?。?/td> 157K
代理商: LC72146
Serial Data Output
The 40-bit data word output on DO has the format and functions as shown in Figure 5 and Table 12, respectively.
Figure 5 Output Data Word Out
Table 12 Input Data Functions
Serial Data Input/Output Mode Selection
The LC72146 use the CCB (computer control bus) serial data format. The first eight bits form the address, shown in
Figure 6, used to select the mode of operation as shown in Table 13.
Table 13 Serial Data Input/Output Mode Selection
No. 4922-13/22
LC72146, 72146M, 72146V
No.
Name
Function
Related bits
Input port data
Bits I1 to I7 reflect the data latched into each input port when the device changes to data output mode.
I6 and I7 are zero when the corresponding port is a counter input. I1 to I5 correspond to the I/O-1 to I/O-5
ports, and I6 and I7, to the HCTR/I-6 and LCTR/I-7 inputs, respectively.
Counter contents
Bits C0 to C19 are the latched contents of the 20-bit binary counter. C19 is the MSB. C0 is the LSB.
(1)
I1 to I7
(2)
C0 to C19
I/O-1 to I/O-5, H/I-6,
L/I-7
OUT1 to OUT5
CTS0, CTS1, CTE
Input/output mode
Address
Function
B0
B1
B2
B3
A0
A1
A2
A3
IN1
0
1
0
1
0
32-bit control data input
IN2
1
0
1
0
1
0
32-bit control data input
OUT
0
1
0
1
0
1
0
Output data. Data is output if the clock is active.
Address
First Data OUT
DI
DO
0
I7
I6
I5
I4
I3
I2
I1
(1)
IN-POR
T
(2)
U-CTR
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
1
0
1
0
1
0
: Data 0
B0
CE
CL
DI
DO
B1
B2
B3
A0
A1
A2
A3
I/O mode determined
First Data IN1/2
First Data OUT
Figure 6 Mode Selection Address Bits
相關(guān)PDF資料
PDF描述
LC72146V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72146M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72147V PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24
LC72148V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72191M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
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