參數(shù)資料
型號: LC72146
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDIP24
封裝: SDIP-24
文件頁數(shù): 8/22頁
文件大?。?/td> 157K
代理商: LC72146
Note: * CTC = 0: 40 mVrms
CTC = 1: 70 mVrms
However, the frequency ranges will be as follows when CTC is 1.
HCTR: 8 to 12 MHz, LCTR: 400 to 500 kHz
Integrating Count
Note: CTE: 0
General-purpose counter reset
1
General-purpose counter start
Restarts on a new 1 setting
In integrated count mode, the count value is accumulated in the general-purpose counter.
Care is required to handle counter overflow.
Counter values: 0H to FFFFFH (1,048,575)
To implement the integrating count operation leave CTE set to 1. When the serial data (IN1) is transmitted again, the general-purpose counter will
start to measure the input again and the result will be added to the count.
No. 4922-16/22
LC72146, 72146M, 72146V
CTS1
CTS0
Input pin
Measurement mode
Frequency range
Input sensitivity
S1
1
HCTR
Frequency
0.4 to 25.0 MHz
40 mVrms*
S2
0
1
LCTR
Frequency
10 to 500 kHz
40 mVrms*
S3
0
LCTR
Period
1.0 to 20
× 103 Hz
(pulse)
GT1
GT0
Frequency measurement mode
Period measurement
Measurement time (ms)
Wait time (ms)
mode
0
4
3 to 4
One period
0
1
8
1
0
32
7 to 8
Two periods
1
64
CE
HCTR
LCTR
Frequency
Measurement
time
Wait time
Measurement
time
One period
VDD
VSS
Period
Measurement
time
900 kHz (check signal)
At least 40 mVrms*
(during frequency
measurement)
CTC = 0 : 40 mVrms
CTC = 1 : 70 mVrms
Note: *
However, the frequency
ranges will be as follows
when CTC is 1.
HTCR : 8 to 12 MHz,
LCTR : 400 to 500 kHz
2.2 V (min)
0.8 V (max)
(during period measurement)
Signal input
CE
GT
end-UC
(DO)
General-purpose
counter
Count complete
Internal data
latch (CTE)
CTE = 1
CTE = 0
Start
(Integration)
Restart
Reset
相關(guān)PDF資料
PDF描述
LC72146V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72146M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72147V PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24
LC72148V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
LC72191M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
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