參數(shù)資料
型號: LC72147V
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24
封裝: SSOP-24
文件頁數(shù): 18/22頁
文件大?。?/td> 154K
代理商: LC72147V
No. 6675-5/22
LC72147V
Pin Functions
Pin No.
Symbol
Usage
Function
Pin circuit
Crystal oscillator connection.
(4.5, 7.2, 10.25, or 10.35 MHz)
1
24
XIN
XOUT
X’tal OSC
FMIN is selected by setting DVS in the control data to 1.
Input frequency: 10 to 180 MHz
The signal is transmitted to the swallow counter.
The divisor can be set to a value in the range 272 to 65,535.
12
FMIN
Local oscillator signal input
This pin must be set to the high level when inputting serial data to the
LC72147V DI pin and when outputting serial data from the DO pin.
23
CE
Chip enable
S
Data synchronization clock signal used when inputting serial data to
the LC72147V DI pin and when outputting serial data from the DO pin.
21
CL
Clock
S
Serial data input for transferring data from the controller to the
LC72147V.
22
DI
Input data
S
Serial data output for transferring data from the LC72147V to the
controller.
20
DO
Output data
LC72147V power supply. A voltage in the range 4.5 to 6.5 V must be
provided when the PLL circuit is operating.
The power-on reset circuit operates when power is first applied.
———
4
VDD
Power
Regulator output. A capacitor must be inserted between Vreg and
VSS.
The output voltage (3.0 V ±10%) is supplied to internal circuits.
5
Vreg
Regulator output
LC72147V ground.
6
VSS
Ground
The LC72147V can control the LA1783/1750 IF buffer output.
This is a 3-state output. (0 V, Vreg/2 = 1.5 V, and Vreg = 3 V)
14
IFBC
IF buffer control
General-purpose I/O ports.
The outputs are open-drain circuits.
After the power-on reset, I/O-1 and I/O-2 function as input ports. I/O-
3 functions as an output port fixed at the low level.
The input/output state of these ports can be set using the I/O-1 to
I/O-3 bits in the serial data sent from the controller.
16
17
2
I/O-1
I/O-2
I/O-3
General-purpose I/O ports
Continued on next page.
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