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參數(shù)資料
| 型號(hào)： | LC72147V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數(shù)： | 22/22頁 |
| 文件大小： | 154K |
| 代理商： | LC72147V |
No. 6675-9/22
LC72147V
DI control data description
No.
Control block/data
Content
Related data
This data sets the divisor for the programmable divider
P0 is the LSB, and P15 is the MSB of this binary value.
DVS = 0: The FMIN pin is pulled down.
1: Selects the FMIN pin.
Divisor setting (N): 272 to 65,536
Input frequency range: 10 to 180 MHz
*: See the “Programmable Divider Structure” item for details.
(1)
Programmable divider data
P0 to P15
DVS
This data controls the sub-charge pump.
(* : don’t care)
*: The sub-charge pump output is connected internally to the gate of the transistor used for
low-pass filter formation. The sub-charge pump can be used in conjunction with the PD
pin (main charge pump pin) to form a high-speed locking circuit.
See the “Charge Pump Structure” item for details.
UL0, UL1, DLC
(2)
Sub-charge pump control data
PDC0, PDC1
Reference frequency selection data
Notes: 1. Illegal value when a crystal oscillator frequency of 10.25 or 10.35 MHz is selected.
2. Illegal value when a crystal oscillator frequency of 10.25 MHz is selected.
3. PLL inhibit (backup mode)
The programmable divider block is stopped, the FMIN pin is pulled down to ground, and
the charge pump output is set to the floating state.
(3)
Reference divider data
R0 to R3
PDC1
PDC0
Sub-charge pump state
0
*
High impedance
1
0
Charge pump operating (PLL unlocked)
1
Charge pump operating (normal operation)
R3
R2
R1
R0
Reference frequency (kHz)
0
100 *1
0001
50
0010
25
0011
25
0
1
0
12.5
0
1
0
1
6.25
0
1
0
3.125
0
1
3.125
1000
10
1001
9 *2
1010
5
1011
1
1100
3 *2
1101
30 *2
1110
*3 PLL inhibit + X’tal OSC stop
1111
*3 PLL inhibit
Continued on next page.
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