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參數(shù)資料
| 型號(hào)： | LC72147V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大小： | 154K |
| 代理商： | LC72147V |
No. 6675-10/22
LC72147V
Continued from preceding page.
No.
Control block/data
Content
Related data
Data that determines the output of the DO and I/O-5 pins
end-AD: A/D converter operation completion
end-UC: General-purpose counter operation completion
However, if I/O-1 and I/O-2 are set to output mode, they go to the open state.
Note: 2. Invalid if the I/O-5 pin is set to input mode.
Caution: Cannot be used in crystal oscillator stop mode (The DO pin will not change state.)
[When the reference divider data is R3 = R2 = R1 = 1, and R0 = 0.]
(4)
DO, I/O-5 pin control data
ULD
DT0, DT1
IL0, IL1
OUT5
I/O-1
I/O-2
I/O-5
A/D converter conversion start data
ADS = 1: Resets and starts the A/D converter
ADS = 0: Resets the A/D converter
If both the ADC0 and ADC1 pins are specified as A/D converter inputs, the levels are
converted sequentially in the order ADC0 first and the ADC1. See the “A/D Converter
Structure” item for details.
(5)
A/D converter control data
ADS
ADI0
ADI1
ULD
DT1
DT0
DO pin
I/O-5 pin
0
Low when unlocked
0
1
end-AD
OUT5 *2
0
1
0
end-UC
011
IN *1
1
0
Open
1
0
1
end-AD
Low when unlocked *2
1
0
end-UC
111
IN *1
IL1
IL0
IN
0
Open
0
1
I-1 (pin state)
1
0
I-2 (pin state)
1
DO goes low when I-1 changes. *
ADI1
ADI0
A/D converter input pin
1
Stopped
1
0
ADC0
0
1
ADC1
0
ADC0, ADC1
CE : Hi
Completion (I-1 change)
Start
DO
Continued on next page.
Note: 1.
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