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參數(shù)資料
| 型號： | LC72711LW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大小： | 157K |
| 代理商： | LC72711LW |
LC72711W, 72711LW
No.6167-18/26
Continued from preceding page.
This means that data that was fully corrected by horizontal correction is not output. Also, packet data that could
not be corrected by either horizontal correction or vertical correction is not output. Furthermore, post-vertical
correction parity packet data is also not output.
(4) Applications can clear the INT signal selection conditions described in (2) and (3) above by setting bit 5
(INT_MOVE) in the control register.
(5) Vertical correction is performed when all of the packet data in a frame is received in frame synchronization and
furthermore when it was not possible to correct all of the packet (block) data with horizontal correction.
Vertical correction is not performed if one frame of data with no errors was received or the receiver was not in
frame synchronization during reception.
To prevent incorrect correction, error correction using vertical correction is not performed for packets error
correction using horizontal correction fully completed and for packets that had no errors.
(6) Under the default settings, if vertical correction is not performed, the corresponding post-vertical correction output
is not output.
Applications can specify the post-vertical correction data to be output regardless of whether or not vertical
correction is performed by setting bit 2 (VEC_OUT) in control register 2.
Note 1. In this case, if data with absolutely no errors is received, completely identical data will be output twice,
once as horizontal correction output, and once as vertical correction output. This status is identical to the
output status of the LC72700E.
Note 2. Immediately after power is applied, undefined data that is, in principle, not required by applications, will
be output as post-vertical correction data.
CPU Interface Basic Limitations
To save internal memory, this IC limits its output data buffer to the smallest size possible. Since the data received by the
IC is written to memory continuously without interruption, the post-correction data in the output data buffer that should
be read out may be overwritten by the following data if readout of the data is delayed.
The output timing for post-correction data, both horizontal and vertical, is stipulated as follows for this IC.
(1) When the IC completes preparation of the output data, it drops the INT pin to the low level as a transfer request.
(2) During data output, there are periods when only horizontal data can be read out, and there are other periods when
both horizontal data and vertical data can be read out in a time-division multiplexed manner.
(3) Applications must complete the data transfer operation within 9ms after the INT pin goes low. If only
post-horizontal correction data is output, the data transfer may be performed within an 18ms period.
After the stipulated period, the next data will be written to the output buffer replacing the previous data, even if
the CPU is reading out the data.
(4) The amount of data that can be read for a single transfer request (INT) for each of the horizontal and vertical data
is one block only. The post-vertical correction data is output in order starting with block number 1 after vertical
correction processing completes. The parity block data is not output.
18ms
68s
1ms
INT
Horizontal data only
output
Horizontal data
output period
Horizontal data
output period
Vertical data output period
Horizontal and vertical
data output
Period during which data
retention is not guaranteed
Figure 2 External Interface - Basic Timing
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