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參數(shù)資料
| 型號(hào)： | LC72711LW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 157K |
| 代理商： | LC72711LW |
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LC72711W, 72711LW
No.6167-10/26
DO_MOVE (Valid only when SP is high.)
0: The high state (high impedance) is held at all times other than when data is being output. (default)
1: Operate identically to the LC72700 when changes are linked to the INT signal, i.e. when both INT_MOVE and
VEC_OUT are set to 1.
CRC4_RST
0: (default)
1: Reset the layer 4 CRC detection circuit.
This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.
Control Register 2
Address
Register
R/W
Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
05H
CTL2
W
00H
SUBBLK
BLK_RST
DACK
DREQ
RDY
VEC_OUT
DMA_RD
DMA
DMA (Valid only when SP is low.)
0: Do not use DMA transfer for readout of post-error correction data. (default)
1: Use DMA transfer for readout of post-error correction data.
DMA_RD (Valid only when SP is low.)
0: Use the RD signal as the DMA transfer read control signal. (default)
1: Use the DACK signal as the DMA transfer read control signal.
VEC_OUT
0: Do not perform post-horizontal correction output when vertical correction processing is not performed. (default)
1: Output all data, even when vertical correction processing is not performed. (Operation identical to that of the
LC72700E)
When this flag is set and a frame of data with absolutely no errors is received, data that is completely identical to
the corresponding post-horizontal correction data is output with the timing of the output of post-vertical correction
data, even if vertical correction is not performed.
This flag must be set to create interface specifications identical to those of the LC72700.
RDY (Valid only when SP is low.)
0: The RDY output is issued with timing 1. (default)
1: The RDY output is issued with timing 2.
DREQ (Valid only when SP is low.)
0: Negative logic is used for the polarity of the DREQ signal. (default)
1: Positive logic is used for the polarity of the DREQ signal.
DACK (Valid only when SP is low.)
0: Negative logic is used for the polarity of the DACK signal. (default)
1: Positive logic is used for the polarity of the DACK signal.
BLK_RST
0: (default)
1: Resets the block synchronization circuit only.
Sets the block synchronization status to unsynchronized and clears the block synchronization protection counter.
However, note that this has no effect on the frame synchronization functions. Also note that during a
synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high-impedance).
This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.
SUBBLK
0: Normal status. (default)
1: Set to 1 when a substation is temporarily received.
RDY Signal Output Timing
RD
RDY
Timing1
RDY
Timing2
DATn
VALID
OUTPUT
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