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參數資料
| 型號： | LC72714W |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數： | 10/29頁 |
| 文件大?。?/td> | 158K |
| 代理商： | LC72714W |
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LC72714W
No.6871-18/29
Notes on Data Output Timing (Relationship with the received data)
Figure 3 shows the timing relationship between the received data and the interrupt control signal (INT). However, the
delay from the actual received signal due to demodulation operations in MSK demodulation blocks is ignored.
Block synchronization is established by discriminating the BIC code. As shown in figure 3, the data for the nth packet
can be output during reception of the following packet (number n+1).
Figure 4 shows the output timing for post-vertical correction data. In vertical correction, the data for a single frame is
stored in memory and the correction operation is performed if frame synchronization was established and it was not
possible to correct all the packet data in horizontal correction. The timing with which vertical correction is started is the
start of the frame. Horizontal correction is performed for each packet while packets 1 through 28 in the nth frame are
being received, and this data is passed to the CPU interface. Vertical correction is performed for the data from the
previous frame (frame n-1) in the unused time periods during that processing.
The vertical correction data consists of 190 blocks that are output, and this data is output at the rate of one block for
every block received, in order starting at the time the 29th packet (block) is received. Only data from the data blocks in
the FM multiplex broadcast frame structure is output, and the last block (block 190) is output during reception of the
218th block.
As indicated previously (page 18) packet data that was, for example, corrected completely by horizontal correction, is
not output in the vertical correction output data. (The INT signal is not issued.) However, the order in which the
horizontal output is produced is not speeded up by the amount of the packet data that is not output. For example, if data
packets 1 to 100 were corrected by horizontal correction, output of the post-vertical correction packet data for packet
101 will not occur at the reception position of block number 29 in figure 4, but at the reception position for packet data
number 129.
BIC
18ms
300ns max
62.5μs
68μs
Packet n-1
Packet n+1
Packet n data
1ms
Recieved
data
BCK
INT
Data cannot
be guaranteed
Packet n data output
Output period for
packet n+1 data
BCK
FCK
INT
1ms
Output periods for
post-vertical correction
data from the previous
frame.
9ms
62.5μs
18ms
271
Recieved block
signal
272
1
2
3
2
1
28
29
30
31
220
219
218
189
190
First
frame
nth frame
18ms28=504ms
Figure 3 Received Data, Block Synchronization, and Data Output Timing
Figure 4 Post-Vertical Correction Data Output Timing
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