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參數(shù)資料
| 型號(hào)： | LC72P366 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Chip One-Time Programmable PROM Single-Chip PLL Controller |
| 中文描述： | 片上一次性可編程可編程單芯片鎖相環(huán)控制器 |
| 文件頁(yè)數(shù)： | 13/14頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | LC72P366 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)
No. 5544-13/14
LC72P366
Continued from preceding page.
Mnemonic
Operand
Function
Operation
Machine code
1st
2n
D15 14
13
12
11
10
9
8
7
6
5
4
3
2
1
D0
AND
r
M
AND M with r
r
←
(r) AND (M)
M
←
(M) AND I
r
←
(r) OR (M)
M
←
(M) OR I
r
←
(r) XOR I
M
←
(M) XOR I
carry
0
0
1
0
0
0
D
H
D
H
D
H
D
H
D
H
D
H
D
L
D
L
D
L
D
L
D
L
D
L
r
ANDI
M
I
AND I with M
0
0
1
0
0
1
I
OR
r
M
OR M with r
0
0
1
0
1
0
r
ORI
M
I
OR I with M
0
0
1
0
1
1
r
EXL
r
M
Exclusive OR I with r
0
0
1
1
0
1
r
EXLI
M
I
Exclusive OR I with M
0
0
1
1
0
1
I
SHR
r
Shift r right with carry
0
0
0
0
0
0
0
0
1
1
1
0
r
(r)
LD
r
M
Load M to r
r
←
(M)
M
←
(r)
1
1
0
1
0
0
D
H
D
H
D
H
D
L
D
L
D
L
r
ST
M
r
Store r to M
Move M to destinsation [DH, rn]
←
(M)
M referring to r in
the same row
Move M to destinsation M
←
[DH, rn]
M referring to r in
the same row
Move source M referring [DH, DL1]
←
[DH, DL2]
to r to M in the same row
1
1
0
1
0
1
r
MVRD
r
M
1
1
0
1
1
0
r
MVRS
M
r
1
1
0
1
1
1
D
H
D
L
r
MVSR
M1
M2
1
1
1
0
0
0
D
H
D
L
1
D
L
2
MVI
M
I
Move I to M
M
←
I
if M (N) = all “1”,
then skip
1
1
1
0
0
1
D
H
D
H
D
L
D
L
I
TMT
M
N
Test M bits, then skip
if all bits specified
are true
1
1
1
1
0
0
N
TMF
M
N
Test M bits, then skip
if all bits specified
are false
if M (N) = all “0”,
then skip
1
1
1
1
0
1
D
H
D
L
N
JMP
ADDR
Jump to the address
PC
←
ADDR
Stack
←
(PC) + 1
PC
←
Stack
1
0
ADDR (14 bits)
CAL
ADDR
Call subroutine
1
1
0
0
ADDR (12 bits)
RT
Return from subroutine
Return from subroutine PC
←
Stack + 1
and skip
Return from subroutine PC
←
Stack
with bank data
Return from subroutine PC
←
Stack + 1
with bank data and skip BANK
←
Stack
Return from interrupt
0
0
0
0
0
0
0
0
1
0
0
0
RTS
0
0
0
0
0
0
0
0
1
0
1
0
RTB
1
1
1
1
1
1
1
1
1
1
0
0
BANK
←
Stack
RTBS
1
1
1
1
1
1
1
1
1
1
0
1
RTI
PC
←
Stack
BANK
←
Stack
CARRY
←
Stack
(Status reg I) N
←
1
(Status reg I) N
←
0
if (Status reg I) N =
all “1”, then skip
0
0
0
0
0
0
0
0
1
0
0
1
SS
I
N
Set status register
1
1
1
1
1
1
1
1
0
0
0
I
N
RS
I
N
Reset status register
1
1
1
1
1
1
1
1
0
0
1
I
N
TST
I
N
Test status register
true
1
1
1
1
1
1
1
1
0
1
I
N
TSF
I
N
Test status register
false
if (Status reg I) N =
“0”, then skip
1
1
1
1
1
1
1
1
1
0
I
N
TUL
N
Test unlock F/F then
skip if it has not been
set
if Unlock FF (N) =
all “0”, then skip
0
0
0
0
0
0
0
0
1
1
0
1
N
PLL
M
r
Load M to PLL register
PLL reg
←
PLL data
M
←
(Rn reg)
1
1
1
1
1
0
D
H
D
H
D
L
D
L
r
INR
M
Rn
Input register/port
data to M
0
0
1
1
1
0
Rn
OUTR
M
Rn
Output contents of M
to register/port
Rn reg
←
(M)
0
0
1
1
1
1
D
H
D
L
Rn
L
T
B
i
J
S
i
F
i
I
t
L
L
Continued on next page.
I
g
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