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參數(shù)資料
| 型號： | LC72P366 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Chip One-Time Programmable PROM Single-Chip PLL Controller |
| 中文描述： | 片上一次性可編程可編程單芯片鎖相環(huán)控制器 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 154K |
| 代理商： | LC72P366 |
No. 5544-9/14
LC72P366
Continued from preceding page.
Pin No.
Symbol
I/O
I/O type
Function
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52 to
45
HOLD
PH0/ADI0
PH1/ADI1
PH2/ADI2
PH3/ADI3
PI0/ADI4
PI1/ADI5
PJ0
PJ1
PJ2
PJ3
PK0/INT0
PK1/INT1
PK2
PK3
PL0 to PL3
PM0 to PM3
I
I
O
I/O
I/O
Input
Input
N-channel open drain
CMOS push-pull
CMOS push-pull
PLL control and clock stop mode control
Setting this pin low in the hold enabled state disables input to the FMIN and AMIN pins and
sets the EO pin to the high-impedance state.
To enter clock stop mode, set the HOLDEN flag, set this pin low, and execute a CKSTP
instruction.
To clear clock stop mode, set this pin high.
General-purpose input port/A/D converter shared-function pins
The IOS instruction with PWn = 7 or 8 switches the pin function between general-purpose
input ports and A/D converter inputs.
General-purpose input port usage
Specify general-purpose input port usage with the IOS instruction with PWn = 7 or 8 in bit
units.
A/D converter usage
Specify A/D converter usage with the IOS instruction with PWn = 7 or 8 in bit units.
Specify the pin to convert with the IOS instruction with PWn = 1.
Start a conversion with the UCC instruction (b2).
The ADCE flag will be set when the conversion competes.
Note: Executing an input instruction for a port specified for ADI usage will always return
low since input is disabled. These pins must be set up for general-purpose input
port usage before an input instruction is executed.
Input is disabled in clock stop mode.
During the power-on reset, these pins go to the general-purpose input port function.
General-purpose output ports
An external pull-up resistor is required since these pins are open-drain circuits.
In clock stop mode, these pins go to the transistor off state (high level output).
During the power-on reset, these pins are set up as general-purpose output ports and go
to the transistor off state (high level output).
General-purpose I/O/external interrupt shared-function ports
There is no instruction that switches the function of these ports between general-purpose
ports and external interrupt ports. These pins function as external interrupt pins at the point
where the external interrupt enable flag is set.
General-purpose I/O port usage
These pins can be set for input or output in bit units (bit I/O).
The IOS instruction is used to specify input or output in bit units.
External interrupt pin usage
This function can be used by setting the external interrupt enable flags (INT0EN and
INT1EN) in status register 2. The corresponding pin must be set up for input.
To enable interrupt operation, the interrupt enable flag (INTEN) in status register 1 also
must be set.
The IOS instruction with PWn = 3, b1 = INT1, and b0 = INT0 is used to select rising or
falling edge detection.
In clock stop mode, input is disabled and these pins go to the high impedance state.
During the power-on reset, these pins function as general-purpose input ports.
General-purpose I/O ports
The IOS instruction is used to specify input or output.
In clock stop mode input is disabled and these pins go to the high impedance state.
During the power-on reset, these pins function as general-purpose input ports.
Continued on next page.
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