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參數(shù)資料
| 型號(hào)： | LC72P366 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Chip One-Time Programmable PROM Single-Chip PLL Controller |
| 中文描述： | 片上一次性可編程可編程單芯片鎖相環(huán)控制器 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 154K |
| 代理商： | LC72P366 |
No. 5544-5/14
LC72P366
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
I
IH
(1)
I
IH
(2)
XIN : V
I
= V
DD
= 5.0 V
FMIN, AMIN, HCTR, LCTR : V
I
= V
DD
= 5.0 V
Ports A, E, F, G, H, I, K, L, M, and Q,
SNS, HOLD,
HCTR, LCTR, and
with no
pull-down resistor on
port A, V
I
= V
DD
= 5.0 V
With input mode selected for ports
E, F, G, K, L, M, and Q
2.0
5.0
15
μA
4.0
10
30
μA
Input high-level current
I
IH
(3)
3.0
μA
I
IH
(4)
I
IL
(1)
I
IL
(2)
Port A: pull-down resistor present
50
μA
XIN:V
I
= V
SS
FMIN, AMIN, HCTR, LCTR : V
SS
Ports A, E, F, G, H, I, K, L, M, and Q,
SNS, HOLD, HCTR, LCTR, and with no
pull-down resistor on port A, V
I
= V
SS
With input mode selected for ports E, F,
G, K, L, M, and Q
2.0
5.0
15
μA
4.0
10
30
μA
Input low-level current
I
IL
(3)
3.0
μA
Input floating voltage
V
IF
Port A: pull-down resistor present
0.05 V
DD
V
k
k
V
Pull-down resistance
R
PD
(1)
R
PD
(2)
V
H
V
OH
(1)
V
OH
(2)
V
OH
(3)
V
OH
(4)
V
OL
(1)
V
OL
(2)
V
OL
(3)
V
OL
(4)
V
OL
(5)
I
OFF
(1)
I
OFF
(2)
I
OFF
(3)
Port A: pull-down resistor present V
DD
= 5 V
TEST1, TEST2
75
100
200
10
Hysteresis
Ports F, G, and K, LCTR (in period measurement mode)
0.1 V
DD
V
DD
– 2.0
V
DD
– 1.0
V
DD
– 1.0
V
DD
– 1.0
0.2 V
DD
V
DD
– 1.0
Ports B and C: I
O
= –1 mA
Ports D, E, F, G, K, L, M, N, O, P, and Q: I
O
= –1 mA
EO1, EO2, EO3, SUBPD : I
O
= –500 μA
XOUT : I
O
= –200 μA
Ports B and C: I
O
= 50 μA
Ports D, E, F, G, K, L, M, N, O, P, and Q: I
O
= 1 mA
EO1, EO2, EO3, SUBPD : I
O
= 500 μA
XOUT : I
O
= 200 μA
Port J: I
O
= 5 mA
Ports B, C, D, E, F, G, K, L, M, N, O, P, and Q
V
Output high-level voltage
V
V
V
1.0
2.0
V
1.0
V
Output low-level voltage
1.0
1.5
2.0
V
–3.0
+3.0
μA
Output off leakage current
EO1, EO2, EO3, SUBPD
–100
+100
nA
Port J
–5.0
+5.0
μA
A/D conversion error
ADI0 to ADI5 : V
DD
(1)
SNS
–1/2
+1/2
LSB
Rejected pulse width
P
REJ
V
DET
I
DD
(1)
I
DD
(2)
50
μs
Power down detection voltage
3.0
3.5
4.0
V
V
DD
(1) : f
IN
(2) = 130 MHz, Ta = 25C
V
DD
(2): halt mode
*
, Ta = 25C (See figure 1.)
V
DD
= 5.5 V, oscillator stopped
Ta = 25C (See figure 2.)
12
24
mA
0.45
mA
Current drain
I
DD
(3)
5
μA
I
DD
(4)
V
DD
= 2.5 V, oscillator stopped
Ta = 25°C (See figure 2.)
1
μA
Electrical Characteristics
in the Allowable Operating Ranges
Note:
*
Executing 20 STEP instructions every millisecond. With the PLL and counter circuits stopped.
Note: With PB to PG, and PJ to PQ all open.
However, with PE to PG, PK to PM, and PQ selected for output.
Figure 1 I
DD
(2) in Halt Mode
Note: With PA to PQ all open.
Figure 2 I
DD
(3) and I
DD
(4) in Backup Mode
Test Circuit Diagrams
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