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參數(shù)資料
| 型號(hào)： | LCK4953 |
| 英文描述： | Low-Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 98K |
| 代理商： | LCK4953 |
4
Agere Systems Inc.
Data Sheet
November 2001
Low-Voltage PLL Clock Driver
LCK4953
Electrical Characteristics
5-8654.a (F)
Figure 2. Logic Diagram
Power Supply Filtering
The LCK4953 is a mixed-signal product which is susceptible to random noise, especially when this noise is on the
power supply pins. To isolate the output buffer switching from the internal phase-locked loop, the LCK4953
provides separate power supplies for the phase-locked loop (V
DD
A) and for the output buffers (V
DD
). In a digital
system environment, besides this isolation technique, it is highly recommended that both V
DDA
and V
DD
power
supplies be filtered to reduce the random noise as much as possible.
Figure 3 illustrates a typical power supply filter scheme. A filter for the LCK4953 should be designed to target noise
in the 100 kHz to 10 MHz range, due to its susceptibility to noise with spectral content in this range. The RC filter in
Figure 3 will provide a broadband filter with approximately
–
40 dB attenuation for noise with spectral content above
20 kHz. More elaborate power supply schemes may be used to achieve increased power supply noise filtering.
5-9575(F)
Figure 3. Power Supply Filter
PECLCKP
PECLCKN
P
N
FBCLK
PLL CORE
A
Z
/4
A
Z
/4
DIVBY4
A
Z
/2
A
Z
/2
DIVBY2
DIVBY4
DIVBY2
D0
D1
SD
Z
D0
D1
SD
Z
D0
D1
SD
Z
D0
D1
SD
Z
Z
PAD
Z
PAD
Z
PAD
QFB
Q[0:6]
Q7
QFB
Q[0:6]
Q7
PLLEN
VCOSEL
BYPASSB
MROEN
0.01
μ
F
22
μ
F
R
S =
5
—
10
V
DD
V
DDA
LCK4953
0.01
μ
F
3.3 V
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